DC9006A
AND
DC9004B
U
SER
G
UIDE
A
NALOG
D
EVICES
,
I
NC
.
C
ONFIDENTIAL
11
U1
ISL43L210
SC70
IN
1
V+
2
GND
3
NC
4
COM
5
NO
6
ISOOC_RESETn
R8
10k
0201
VCCA
ISOOC_RESETn
MOTE RESET
ISO_MOTE_OFFn
R10
0
0201
NoStuf f
PB1
SPST-NO
SWT3-G
1
2
C49
0.1uF
0201
R83
10k
0201
R38
100k
0201
Q3
DMN2004
SC70-3
1
2
3
VCCA_SW
EXT. JTAG & SWD CONNECTOR
ISOSW_TCK
ISOSW_TMS
ISOSW_TDI
P1
100MIL_VERT_SHR
HDR2X10BOXED
2
4
6
8
1
3
5
7
9
10
12
14
13
11
15
16
17
18
19
20
ISOSW_TDO
R2
0
0201
R9
1k
0201
R3
0
0201
NoStuf f
ISO_MOTE_OFFn
ISO_MOTE_OFFn
Figure 5
External JTAG Pinout, Reset & Vsense Logic
Eterna Evaluation and Development Mote Socket Pinout
The following table shows the pinout of the socket connector to the Eterna
Evaluation and Development Board.
Pin # Signal
Direction
Pin # Signal
Direction
1 UART_TX_CTSn
O
2 UART_TX_RTSn
I
3 UART_TX
I
4 GND
-
5 UART_RX
O
6 UART_RX_RTSn
O
7 UART_RX_CTSn
I
8 UARTC0_TX/UARTC1_TX
I
9 UARTC0_RX/UARTC1_RX O 10 GND
-
11 RESETn
O
12 FLASH_P_ENn
(GPIO2)
I/O
13
IPCS_MISO (GPIO6)
I/O
14
IPCS_MOSI (GPIO5)
I/O
15
IPCS_SSn (GPIO3)
I/O
16
IPCS_SCK (GPIO4)
I/O
17 GND
-
18 TCK
O
19 TMS
O
20 TDO
I
21 TDI
O
22
VUSB_3V6
Power
Out
23
PGOOD
O 24
GND
-
25
VBATTERY
I 26
KEY
NC
27
Reserved (EHORBAT)
I/O 28
Reserved (MOTE_OFF)
I/O
29
Reserved (GPIO1)
I/O 30
Reserved (GPIO2)
I/O
31
V+
Power
Out
32
+5V
Power
Out
Signal direction is relative to the DC9006;
Highlighted signals provide reserved connections for the evaluation of energy harvesting solutions
Connector: Samtec SSW-116-02-F-D or SSW-116-02-F-D-RA-025 (polarized right angle)
Warning:
Connector pin numbering is custom, refer to layout for details.
