Analog Devices ADZS-BF707-BLIP2, Руководство пользователя

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ADZS-BF707-BLIP2 Board Evaluation System Manual 1-9
Using ADZS-BF707-BLIP2 Board
SD Interface
The ADSP-BF707 processor has a secure digital (SD) interface that con-
sists of a clock pin, command pin, card detect pin, and an 8-bit data bus.
Debug Interface
The BLIP2 board provides a JTAG/SWD/SWO connection through a
connector (
P3
), which is a 0.05” pitch header. A 8-bit trace connection
also is available through a connector (
P2
), although this is not supported
at this time. See JTAG/SWD/SWO Connector (P3) for more
information.
Power-On-Self Test
The Power-On-Self-Test Program (POST) tests all BLIP2 board peripher-
als, except for SD card interface, and validates functionality as well as
connectivity to the processor. Once assembled, each BLIP2 board is fully
tested for an extended period of time with POST. All BLIP2 boards are
shipped with Video Occupancy Sensor real-time applications burned into
flash memory. For executing POST code, refer to the Power_On_Self_
Test example in the Board Support Package.
Note that the source code for the POST program is included in the
ADZS-BF707-BLIP2 Board Support Package along with the
readme.txt
file that describes how the board is configured to run POST.
RF Wireless Interface
A RF Wireless connector allows the BLIP2 board to be connected to an
Analog Devices Inc. Wireless Sensor Network (WSN) cluster board
EV-ADRN-WSN-2Z. Alternatively, it can be used as a general-purpose