Analog Devices ADV8005, Справочник по аппаратуре

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ADV8005 Hardware Reference Manual UG-707
Input Output
audio_input
_sel Value
audio_mode
Value I2s_format
Value Audio
Input
Signal
Clock Pins Encoding ADV8005
Input Pin
Mapping
Format Packet Type
0b011 0b01 0b00 I2S[3:0] SCLK,
MCLK
1
Normal AUD_IN[4:0]
SCLK
MCLK Standard
I2S HBR Packet
0b011 0b01 0b01 I2S[3:0] SCLK, MCLK Normal AUD_IN[4:0]
SCLK
MCLK Right
justified HBR Packet
0b011 0b01 0b10 I2S[3:0] SCLK,
MCLK
1
Normal AUD_IN[4:0]
SCLK
MCLK Left justified HBR Packet
0b011 0b01 0b11 I2S[3:0] SCLK,
MCLK
1
Normal AUD_IN[4:0]
SCLK
MCLK AES3 Direct HBR Packet
0b011 0b10 0bXX SPDIF MCLK Biphase
Mark AUD_IN[0]
MCLK IEC61937 HBR Packet
0b011 0b11 0b00 SPDIF SCLK,
MCLK
1
Normal AUD_IN[0]
SCLK
MCLK Standard
I2S HBR Packet
0b011 0b11 0b01 I2S[3:0] SCLK,
MCLK
1
Normal AUD_IN[4:0]
SCLK
MCLK Right
Justified HBR Packet
0b011 0b11 0b10 I2S[3:0] SCLK,
MCLK
1
Normal AUD_IN[4:0]
SCLK
MCLK Left
Justified HBR Packet
0b011 0b11 0b11 I2S[3:0] MCLK Normal AUD_IN[4:0]
MCLK IEC61937 HBR Packet
1
Optional signal
6.11.3.1. I2S Audio
The ADV8005 can receive up to four stereo channels of I2S audio at up to a 192 kHz sampling rate. The number of I2S channels the Tx processes
can be selected with audioif_cc[2:0] . The selection of the active I2S channels is done via the i2s_en[3:0] field. The audio sampling frequency of
the input stream must be set appropriately via the i2s_sf[3:0] field. This value is used along with the VIC to determine the pixel repetition factor
that the Tx core applies to the video data (refer to Section 6.10.3 ). The value programmed in i2s_sf[3:0] is also used to be sent across the TMDS
output link in the channel status data information contained in the Audio Sample packets.
The placement of I2S channels into the Audio Sample subpackets defined in the HDMI specification can be specified in the following fields:
•
subpkt0_l_src
•
subpkt0_r_src
•
subpkt1_l_src
•
subpkt1_r_src
•
subpkt2_l_src
•
subpkt2_r_src
•
subpkt3_l_src
•
subpkt3_r_src
When these fields are set to their default values, all I2S channels are placed in their respective position (for example, I2S0 left channel in channel
0 left position, I2S3 right channel in channel 3 right position, and so on) but this mapping is completely programmable if desired.
The
ADV8005 can receive standard I2S, left-justified, right-justified, and direct AES3 stream formats with a sample word width between 16 bits
and 24 bits. The format of the input I2S stream is set via i2s_format[1:0] while the audio sample word width is set via the word_length[3:0] field.
The ADV8005 can also receive an I2S stream in both 64-bit and 32-bit modes, so either 32- or 16-bit clock (that is, the signal input through
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