ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 155 of 196
GENERAL-PURPOSE TIMERS OPERATION
Free Running Mode
In free running mode, the timer is started by setting the enable bit (TxCON[4]) to 1 and the MOD bit (TxCON[3]) to 0. The timer
increments from zero scale/full scale to full scale/zero scale if counting up/down. Full scale is 2
16
– 1 or 0xFFFF in binary format. Upon
reaching full scale (or zero scale), a timeout interrupt occurs and TxSTA[0] is set. To clear the timer interrupt, user code must write 1 to
TxCLRI[0]. If TxCON[7] is set, the timer keeps counting and reloads when the TxCLRI register is written.
Periodic Mode
In periodic mode, the initial TxLD value should be loaded before starting the timer by setting the enable bit (TxCON[4]) to 1. The timer
value either increments from the value in TxLD to full scale or decrements from the value in TxLD to zero scale, depending on the
TxCON[2] settings (count up/down). Upon reaching full scale or zero scale, the timer generates an interrupt. The TxLD is reloaded into
TxVAL, and the timer continues counting up or down. The timer should be disabled prior to changing the TxCON or TxLD register. If
the TxLD register is changed while the timer is being loaded, undefined results may occur. By default, the counter is reloaded automatically
when generating the interrupt signal. If TxCON[7] is set to 1, the counter is also reloaded when user code writes TxCLRI. This allows
user changes to the TxLD to take effect immediately instead of waiting until the next timeout.
The timer interval is calculated as follows:
If the timer is set to count down,
Interval
= (
TxLD
×
Prescaler
)/
Source Clock
For example, if TxLD = 0x100, prescaler = 4, and clock source = UCLK, the interval is 12.8 µs (where UCLK = 80 MHz).
If the timer is set to count up,
Interval
= ((
Full Scale
−
TxLD
) ×
Prescaler
)/
Source Clock
Asynchronous Clock Source
Timers are started by setting the enable bit (TxCON[4]) to 1 in the control register of the corresponding timer.
However, when the timer clock source is HFXTAL or LFOSC, some precautions must be taken:
•
The control register (TxCON) should not be written if TxSTA[6] is set. Therefore, TxSTA should be read prior to configuring the
control register (TxCON). When TxSTA[6] is cleared, the register can be modified. This ensures that synchronizing the timer control
between the processor and timer clock domains is complete. TxSTA[6] is the timer busy status bit.
•
After clearing the interrupt in TxCLRI, it must be ensured that the register write has fully completed before returning from the
interrupt handler. Use the data synchronization barrier (DSB) instruction if necessary and check that TxSTA[7] = 0.
__asm void asmDSB()
{
nop
DSB
BX LR
}
•
The value of a counter can be read at any time by accessing its value register (TxVAL). In an asynchronous configuration, TxVAL
should always be read twice. If the two readings are different, it should be read a third time to determine the correct value.
TxSTA should be read prior to writing to any timer register after setting or clearing the enable bit. When TxSTA[7] is cleared, registers
can be modified. This ensures that the timer has completed synchronization between the processor and timer clock domains. The typical
synchronization time is two timer clock periods.
The TxCON register enables the counter, selects the mode, selects the prescale value, and controls the event capture function.
