ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 103 of 196
The bit rate is defined in the I2CxDIV MMR as follows:
f
SCL
=
f
I2CCLK
/(
LOW
+
HIGH
+ 3)
where:
f
I2CCLK
=
f
PCLK
/
I2CCD.
f
PCLK
is the peripheral clock, 20 MHz.
I2CCD
is the clock divide value and is set by the CLKCON1[10:8] bits.
HIGH
is the high period of the clock, I2CxDIV[15:8] = (REQD_HIGH_TIME/PCLK_PERIOD) − 2.
LOW
is the low period of the clock, I2CxDIV[7:0] = (REQD_LOW_TIME/PCLK_PERIOD) − 1.
For 100 kHz SCL operation, with a low time of 5 µs, a high time of 5 µs, and a PCLK frequency of 20 MHz,
HIGH
= (5 µs/(1/20,000,000)) − 2 = 98 = 0x62
LOW
= (5 µs/(1/20,000,000)) − 1 = 99 = 0x63
f
SCL
= 20,000,000/(98 + 99 + 3) = 100 kHz
Resetting the I
2
C block
Three steps are needed to reset the I
2
C block.
In master mode,
1.
Clear I2CxMCON[0] to 0. This disables the I
2
C master.
2.
Set I2CxSHCON[0] to 1. This is a write only register. Writing to this bit resets the start/stop detection circuits of the I
2
C block and
clears the LINEBUSY status bit (I2CxMSTA[10]).
3.
Set I2CxMCON[0] = 1 to reenable the I
2
C master.
In slave mode,
1.
Clear I2CxSCON[0] to 0. This disables the I
2
C slave.
2.
Set I2CxSHCON[0] to 1. This is a write only register. Writing to this bit resets the start/stop detection circuits of the I
2
C block.
3.
Set I2CxSCON[0] to 1 to reenable the I
2
C slave
Do not reset the I
2
C peripheral on two consecutive communication sequences.
I
2
C OPERATING MODES
Master Transfer Initiation
If the master enable bit (I2CxMCON[0], MASEN) is set, a master transfer sequence is initiated by writing a value to the I2CxADRx register.
If there is valid data in the I2CxMTX register, it is the first byte transferred in the sequence after the address byte during a write sequence.
Slave Transfer Initiation
If the slave enable bit (I2CxSCON[0], SLVEN) is set, a slave transfer sequence is monitored for the device address in Register I2CxID0,
Register I2CxID1, Register I2CxID2, or Register I2CxID3. If the device address is recognized, the part participates in the slave transfer sequence.
Note that a slave operation always starts with the assertion of one of three interrupt sources—read request (MRXREQ/ SRXREQ), write
request (MTXREQ, STXREQ), or general call (GCINT) interrupt—and the software should always look for a stop interrupt to ensure that
the transaction has completed correctly and to deassert the stop interrupt status bit.
Rx/Tx Data FIFOs
The transmit datapath consists of a master and slave Tx FIFO, I2CxMTX and I2CxSTX, that are each two bytes deep and a transmit
shifter. The transmit status bits in I2CxMSTA[1:0] and I2CxSSTA[0] denote whether there is valid data in the Tx FIFO. Data from the Tx
FIFO is loaded into the Tx shifter when a serial byte begins transmission. If the Tx FIFO is not full during an active transfer sequence, the
transmit request bit (I2CxMSTA[2] or I2CxSSTA[2]) asserts.
In the slave, if there is no valid data to transmit when the Tx shifter is loaded, the transmit underflow status bit asserts (I2CxMSTA[12],
ISCxSSTA[1]).
The master generates a stop condition if there is no data in the transmit FIFO and the master is writing data.
The receive datapath consists of a master and slave Rx FIFO, I2CxMRX and I2CxSRX, that are each two bytes deep. The receive request
interrupt bit (I2CxMSTA[3] or I2CxSSTA[3]) indicates whether there is valid data in the Rx FIFO. Data is loaded into the Rx FIFO after
each byte is received. If valid data in the Rx FIFO is overwritten by the Rx shifter, the receive overflow status bit (I2CxMSTA[9] or I2CxSSTA[4])
is asserted.
