ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 135 of 192
In slave mode, the SPIxCON register must be configured with the phase and polarity of the expected input clock. The slave accepts data
from an external master at rates of up to 20 Mbps.
In both master and slave modes, data is transmitted on one edge of the SCLK signal and sampled on the other. Therefore, it is important
that the polarity and phase be configured the same for the master and slave devices.
Chip Select (CS Input) Pin
In SPI slave mode, a transfer is initiated by the assertion of CS, which is an active low input signal. The SPI port then transmits and
receives 8-bit data until the transfer is concluded by the deassertion of CS. In slave mode, CS is always an input.
In SPI master mode, CS is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon
completion.
CS must always be configured as an SPI pin in GPxCON when the SPI is used. If an
master wants to communicate with
multiple SPI slaves, CS must be left floating, and the GPIOs can be connected to the CS lines of the slaves. The CSRSG and CSFLG bits in
the SPIxSTA register (Bits[14:13]) can determine the right time to bring the GPIOs low and high.
SPI TRANSFER INITIATION
In master mode, the transfer and interrupt mode bit, TIM (SPIxCON[6]), determines the manner in which an SPI serial transfer is
initiated. If the TIM bit is set, a serial transfer is initiated after a write to the Tx FIFO. If the TIM bit is cleared, a serial transfer is initiated
after a read of the Rx FIFO; the read must be performed while the SPI interface is idle. A read performed during an active transfer does
not initiate another transfer.
For any setting of SPIxCON[1] and SPIxCON[6], the SPI simultaneously receives and transmits data. Therefore, during data transmission,
the SPI is also receiving data and filling up the Rx FIFO. If the data is not read from the Rx FIFO, the overflow interrupt occurs when the
FIFO starts to overflow. If the user does not want to read the Rx data or receive overflow interrupts, SPIxCON[12] can be set, and the
receive data is not saved to the Rx FIFO.
Similarly, when the user wants to only receive data and does not want to write data to the Tx FIFO, SPIxCON[13] can be set to avoid
receiving underrun interrupts from the Tx FIFO.
Tx Initiated Transfer
For transfers initiated by a write to the Tx FIFO, the SPI starts transmitting as soon as the first byte is written to the FIFO, irrespective of
the configuration in SPIxCON[15:14]. The first byte is immediately read from the FIFO, written to the Tx shift register, and the transfer
commences.
If the continuous transfer enable bit, SPIxCON[11], is set, the transfer continues until no valid data is available in the Tx FIFO. There is
no stall period between transfers where CS is deasserted; CS is asserted and remains asserted for the duration of the transfer until the Tx
FIFO is empty. Determining when the transfer stops does not depend on SPIxCON[15:14]; the transfer stops when there is no valid data
left in the FIFO. Conversely, the transfer continues while there is valid data in the FIFO.
If the continuous transfer enable bit, SPIxCON[11], is cleared, each transfer consists of a single 8-bit serial transfer. If valid data exists in
the Tx FIFO, a new transfer is initiated after a stall period where CS is deasserted.
Rx Initiated Transfer
Transfers initiated by a read of the Rx FIFO depend on the number of bytes to be received in the FIFO. If SPIxCON[15:14] = 11 and a read to the
Rx FIFO occurs, the SPI initiates a 4-byte transfer. If continuous mode is set, the four bytes occur continuously with no deassertion of CS
between bytes. If continuous mode is not set, the four bytes occur with stall periods between transfers where the CS is deasserted. A read
of the Rx FIFO while the SPI is receiving data does not initiate another transfer after the present transfer is complete.
In slave mode, a transfer is initiated by the assertion of CS (CS = 0).
The device as a slave transmits and receives 8-bit data until the transfer is concluded by the deassertion of CS (CS = 1).
The SPI transfer protocol diagrams (see Figure 24 and Figure 25) illustrate the data transfer protocol for the SPI and the effects of the
CPHA and CPOL bits in the control register (SPIxCON) on that protocol.
