ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-7
EZ-KIT Lite Hardware Reference
Video Output (PPI1)
The
PPI1
interface is configured as output and connects to the on-board
video encoder device, ADV7179. The ADV7179 encoder generates three
analog video channels on
DAC A
,
DAC B
, and
DAC C
. The
PPI1
bits
7
–
0
con-
nect to
P7
–
0
of the encoder’s pixel inputs. The encoder’s input clock is
fixed and comes from an on-board 27 MHz oscillator.
The encoder’s synchronization signals,
HSYNC
and
VSYNC
, can be config-
ured as inputs or outputs. Video Blanking control signal is at level “
1
”.
The
HSYNC
and
VSYNC
signals can connect to the ADSP-BF561 processor’s
PPI1
interface
SYNC1
and
SYNC2
via the
SW2
switch, as described in
Configuration Switch (SW2)” on page 2-10
PPI0
SYNC2
Timer 9
ADV7179
VSYNC
. For more information, see
Configuration Switch (SW2)” on page 2-10
PPI0
Clock
A choice of ADV7183A output clock, a local 27 MHz
oscillator, or an external clock from
ADSP-BF533/BF561 EZ-KIT Extender 1 board.
PPI1
SYNC1
Timer 10
ADV7183A HSYNC. For more information, see
“Video Configuration Switch (SW2)” on page 2-10
PPI1 SYNC2
Timer 11
ADV7183A
VSYNC
. For more information, see
Configuration Switch (SW2)” on page 2-10
PPI1
Clock
A choice of ADV7183A output clock, a local 27 MHz
oscillator, or an external clock from
ADSP-BF53x/BF561 EZ-Extender 1.
Table 2-2. PPI Connections (Cont’d)
Processor PPI
Pin
Other PRocessor
Function
EZ-KIT Function
Содержание ADSP-BF561 EZ-KIT Lite
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