ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-11
Using EZ-KIT Lite
The AD1836A codec reset is controlled by the processor’s programmable
flag
PF15
. When
PF15
is “
0
”, the reset is asserted. When
PF15
is “
1
”, the
reset is de-asserted. Note, when
PF15
is not driven (configured as input),
the AD1836A reset is asserted due to the pull-down resistor. See
for more information.
L
Example programs are included in the EZ-KIT installation direc-
tory to demonstrate the AD1836A codec operation.
Video Interface
The board supports video input and output applications. The ADV7179
video encoder provides up to three output channels of analog video, while
the ADV7183A video decoder provides up to three input channels of ana-
log video. The video encoder connects to the Parallel Peripheral
Interface 1 (
PPI1
), while the video decoder connects to the Parallel
Peripheral Interface 0, (
PPI0
). Each PPI interface has an individual clock
that is configured by the
SW5
switch settings. See
Both the encoder and the decoder connect to the Parallel Peripheral Inter-
faces (PPI input clock) of the ADSP-BF561 processor. For additional
information on the video interface hardware, refer to
For the video interface to be operational, the following basic steps must be
performed.
1. Configure the
SW2
DIP switch as required by the application. Refer
to
“Video Configuration Switch (SW2)” on page 2-10
for details.
2. De-assert the video device’s reset by setting a corresponding pro-
grammable flag “
High
”. Note that
PF14
controls the ADV7179
encoder’s reset, while
PF13
controls the ADV7183A decoder’s
reset.
Содержание ADSP-BF561 EZ-KIT Lite
Страница 4: ......
Страница 40: ...VisualDSP Interface 1 18 ADSP BF561 EZ KIT Lite Evaluation System Manual ...
Страница 62: ...Connectors 2 22 ADSP BF561 EZ KIT Lite Evaluation System Manual ...