Analog Devices ADSP-21591, Руководство пользователя

Страница: 13 / 32

commands that transfer addresses and read data on both edges of the clock.These transfer rates can outperform 16-
bit Parallel Flash memories, allowing for efficient memory access to support XIP (eXecute In Place) operation.
The memory array is organized into programmable pages of 256/512 bytes. This family supports page program
mode where 1 to 256/512 bytes of data are programmed in a single command.
QPI (Quad Peripheral Interface) supports 2-cycle instructions, further reducing instruction times. Pages can be
erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64K/256Kbyte blocks, and/or the entire chip. The uniform sec-
tor and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety
of applications requiring solid data retention.
IS43TR16512BL - 1Gx8, 512Mx16 8Gb DDR3 SDRAM
•
Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V - Backward compatible to 1.5V
•
High speed data transfer rates with system frequency up to 933 MHz
•
8 internal banks for concurrent operation
•
8n-Bit pre-fetch architecture
•
Programmable CAS Latency
•
Programmable Additive Latency: 0, CL-1,CL-2
•
Programmable CAS WRITE latency (CWL) based on tCK
•
Programmable Burst Length: 4 and 8
•
Programmable Burst Sequence: Sequential or Interleave
•
BL switch on the fly
•
Auto Self Refresh(ASR)
•
Self Refresh Temperature(SRT)
•
Refresh Interval: 7.8 µs (8192 cycles/64 ms) Tc= -40°C to 85°C 3.9 µs (8192 cycles/32 ms) Tc= 85°C to 95°C
1.95 µs (8192 cycles/16 ms) Tc= 95°C to 105°C 0.97 µs (8192 cycles/8 ms) Tc= 105°C to 115°C
•
Partial Array Self Refresh
•
Asynchronous RESET pin
•
TDQS (Termination Data Strobe) supported (x8 only)
•
OCD (Off-Chip Driver Impedance Adjustment)
•
Dynamic ODT (On-Die Termination)
•
Driver strength : RZQ/7, RZQ/6 (RZQ = 240
Ω
)
•
Write Leveling
IS43TR16512BL - 1Gx8, 512Mx16 8Gb DDR3 SDRAM
2–6
EV-21593-SOM
®
Manual