
ADSP-2126x SHARC Processor Hardware Reference
9-3
Serial Ports
telephony interfaces. In multichannel mode, SPORT0 and
SPORT1 work as a pair, SPORT2 and SPORT3 work as a pair,
and SPORT4 and SPORT5 work as a pair. See
When programming the serial port channel (A or B) as a transmit-
ter, only the corresponding transmit buffers
TXSPxA
and
TXSPxB
become active, while the receive buffers (
RXSPxA
and
RXSPxB
)
remain inactive. Similarly, when SPORT channels A and B are pro-
grammed to receive, only the corresponding
RXSPxA
and
RXSPxB
buffers are activated.
SPORTs are forced into pairs when in multichannel mode.
more information, see “Multichannel Operation” on page 9-24.
• The serial ports are configurable for transferring data words
between 3 and 32 bits in length, either most significant bit (MSB)
first or least significant bit (LSB) first. Words must be between 8
and 32 bits in length for I
2
S and Left-justified Sample Pair mode.
Refer to
“Data Word Formats” on page 9-39
and the individual
SPORTs operation mode sections for additional information.
• 128-channel TDM is supported in multichannel mode operation,
described in
“Multichannel Operation” on page 9-24
.
Receive comparison and 2-dimensional DMA are not supported in
the ADSP-2126x.
The
SPTRAN
bit in the
SPCTLx
register affects the operation of the transmit
or the receive data paths. The data path includes the data buffers and the
shift registers. When
SPTRAN
= 0, the primary and secondary
RXSPxy
data
buffers and receive shift registers are activated, and the transmit path is
disabled. When
SPTRAN
= 1, the primary and secondary
TXSPxy
data buf-
fers and transmit shift registers are activated, and the receive path is
disabled.
Содержание ADSP-21261 SHARC
Страница 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Страница 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Страница 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Страница 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Страница 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...