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ADSP-2126x SHARC Processor Hardware Reference
5-3
Memory
than the Von Neumann architecture provides, many DSPs use memory
architectures that have separate data and address buses for program and
data storage. These two sets of buses let the DSP retrieve a data word and
an instruction simultaneously. This type of memory architecture is called
Harvard architecture.
SHARC DSPs go a step further by using a Super Harvard architecture.
This four bus architecture has two address buses and two data buses, but
provides a single, unified address space for program and data storage.
While the Data Memory (DM) bus only carries data, the Program Mem-
ory (PM) bus handles instructions and data, allowing dual-data accesses.
Processor core and I/O processor accesses to internal memory are
completely independent and transparent to one another. Each
block of memory can be accessed by the DSP core and I/O proces-
sor in every cycle—no extra cycles are incurred if the DSP core and
the I/O processor access the same block.
A memory access conflict can occur when the processor core attempts two
accesses to the same internal memory block in the same cycle. When this
conflict, known as a block conflict occurs, an extra cycle is incurred. The
DM bus access completes first and the PM bus access completes in the fol-
lowing (extra) cycle.
For more information on how the buses access memory blocks, see
.
Buses
As shown in
, the processor has three sets of internal buses con-
nected to its dual-ported memory, the Program Memory (PM), Data
Memory (DM), and I/O Processor (I/O) buses. The PM and DM buses
share one memory port and the I/O bus connects to the other port. Mem-
ory accesses from the DSP’s core (computational units, data address
generators, or program sequencer) use the PM or DM buses, while the I/O
Содержание ADSP-21261 SHARC
Страница 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Страница 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Страница 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Страница 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Страница 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...