5.8 EMAFE
The indexed addressing required by the EMAFE interface is implemented through the
CPLD. The CPLD controls the loading of the address, as well as the data direction of the
data bus. As with the UART, the address is only partially decoded. The aliasing seen with the
UART also exists with the EMAFE interface in the MS1 address space.
On the ADSP-21065L, data is valid when the WR line goes high. If an address hold cycle is
enabled (in the WAIT register), the data stays valid through the WR transition.
The parallel communication between the ADSP-21065L processor on the evaluation
board and the EMAFE consists of some control logic for the control lines (MC, RD, WR, CS,
etc.), an 8-bit latch that stores the address information (MA[7:0]) and a transceiver buffer for the
data lines (MD[15:0]). The address lines are latched and the data lines are buffered to reduce
digital noise on the EMAFE board. The serial ports from the ADSP-21065L are directly wired to
the EMAFE connector interface pins. Level shifting of serial port signals from the ADSP-21065L
may be required for 5V (non 3.3V compliant) peripherals on the EMAFE board, or from 5V
peripherals on the EMAFE board to the 3.3v (non 5V tolerant) ADSP-21065L. For information
on EMAFE pins, see “EMAFE Expansion” in Chapter 6.
5.9 AD1819
As with the UART, the AD1819 is a 5V device. To prevent over driving the SPORT lines on the
ADSP-21065L, the lines from the AD1819 are buffered through a 74LVT125. This buffer has the
additional purpose of bypassing the AD1819’s control of SPORT1, when SPORT1 is required by
the EMAFE. This is done to prevent contention between the two devices on the SPORT1 lines.
On power up, the AD1819 reads the
SDATA_OUT
signal line. If the pin is high or floating, the
AD1819 enters a test mode. To prevent the AD1819 from entering this mode, a pull down
resistor has been added to the line.
5.10 SDRAMS
The processor’s SDRAM interface enables it to transfer data to and from synchronous
DRAM (SDRAM) at 2xCLKIN. The synchronous approach coupled with 2xCLKIN frequency
supports data transfer at a high throughput—up to 240 Mbytes/sec. All inputs are
sampled and all outputs are valid at the rising edge of the clock SDCLK. Table 5-8 lists and
describes the processor’s SDRAM pins and their connections.
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