Figure 3-1
ADSP-21065L EZ-KIT Lite Monitor Kernel Codec Transfer Scheme
3.3.3.2.1 DSP/Codec Transmit Sequence
1.
The SPORT1 transmit DMA empties the transmit buffer, a SPORT1 transmit
interrupt occurs.
2.
If the variable Tx Request > 0, then the interrupt loads the data from the User
Tx Buffer into the Tx Buffer; otherwise, the Tx Buffer is loaded with 0s.
3.
After the Tx Buffer is loaded, the DMA is re-initialized to transmit the new data
in the Tx Buffer.
4.
With this structure set up by the monitor, the user needs to only put data in the
User Tx Buffer, and then set Tx Request to 1, to send data to the codec.
3.3.3.2.2 DSP/Codec Receive Sequence
1. The receive portion of the codec interface is designed in a similar way to the
transmit portion.
2. The DMA for SPORT1's receive register is configured to load the Rx Buffer.
3. When the Rx Buffer is full, an interrupt is forced that checks the Rx Request
variable. If the variable > 0 then the contents of the Rx Buffer is written into the
User Rx Buffer, and the Rx Request is cleared.
4. The DMA is re-initialized to fill the Rx Buffer again.
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