ADSP-21992 EZ-KIT Lite Evaluation System Manual
4-32
4.2.4 Reference Voltage Generation
The ADSP-21992 EZ-KIT Lite board contains an external voltage reference, the LM4140-1.0
(U3), which provides a precise 1.024V output. The ADSP-21992 EZ-KIT Lite board can be
configured to operate from the internal (ADSP-21992 generated) or the external voltage
reference. Two jumpers control the selection of the internal or external voltage reference.
Jumper JP3 ties the SENSE pin of the ADSP-21992 to the AVDD or GND levels. Connecting
SENSE to AVDD (JP3 in position 2-3) selects external voltage reference operation. In this mode,
the ADSP-21992 accepts an input voltage reference at the VREF pin. To connect the external
voltage reference to the ADSP-21992 on the evaluation board, to close the JP4 jumper. This
connects the external voltage reference from the LM4140-1.0 to the VREF pin of the ADSP-
21992. The signal, which is buffered using an operational amplifier OP193 (A11), level-shifts the
applied analog input signals on the analog inputs connector, P4, (as well as being connected to the
ASHAN and BSHAN inputs to the sample-and-hold amplifiers).
To operate with the internally derived voltage reference of the ADSP-21992, the JP3 jumper must
be tied in position 1-2 to connect the SENSE pin to AGND. Additionally, jumper JP4 must be left
open. The ADSP-21992 provides a 1V reference at the VREF pin that is buffered and applied to
the ASHAN and BSHAN inputs. The buffered VREF signal is also used in the level-shifting
circuitry.
In summary, the appropriate settings for jumpers JP3 and JP4 for internal and external voltage
reference operation are:
INTERNAL Reference: JP3 in position 1-2, JP4 open
EXTERNAL Reference: JP3 in position 2-3, JP4 closed
See page 4-39 for more information.
4.2.5 External Memory Interface (EMI)
A 64K by 16-bit SRAM IC (U8) is provided on the External Memory Interface (EMI) of the
ADSP-21992 EZ-KIT Lite board.
Sockets are provided on the ADSP-21992 EZ-KIT Lite board so that the EMI can also be
connected to two 512K x 8-bit flash memory ICs (U5, U6). These flash memory ICs are
connected to the boot memory select pin (
BMS)
and the memory select 0 pin (
MS0
), allowing the
flash memory to boot the DSP as well as store information during normal operation. 8-bit wide
(and 16-bit, if implemented in boot ROM) booting is possible. Refer to section
for
information about the location of the flash memory in the DSP’s memory map.
Jumpers are provided to allow mapping RAM into different banks, and a two input AND gate,
with a jumper, allows for mapping flash into boot memory space or
MS0
.
