Analog Devices AD9166-FMC-EBZ, Руководство пользователя

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UG-1698 AD9166-FMC-EBZ User Guide
Rev. 0 | Page 18 of 23
JESD204B LANE MAPPING OF THE AD9166-FMC-
EBZ EVALUATION BOARD
The ADS7-V2EBZ is based on a Xilinx® Virtex®7 FPGA device.
The user can configure another Xilinx Virtex7-based evaluation
board to drive the AD9166-FMC-EBZ evaluation board. The
JESD204B parameters are available in the
AD9166 data sheet.
The physical lanes on the FMC connector are not necessarily
connected to the same lane numbers as on the
AD9166 . The
AD9166 has a crossbar switch that allows remapping the logical
lanes of the JESD204B core to the correct physical lanes.
However, in the case of the
ADS7-V2EBZ and the AD9166 , the
adjustment is made using the crossbar in the Xilinx JESD204B
transmitter.
The following list is the mapping between the FMC lanes and
the
AD9166 lanes on the AD9166-FMC-EBZ evaluation board.
The mapping to the Xilinx JESD204B intellectual property (IP)
is also provided in the following list for reference:

Physical Lane 0 on the FMC connector (DP0_C2M) is also
Lane 0 on the
AD9166 (Lane 0 of the Xilinx JESD204B IP)

Physical Lane 1 on the FMC connector (DP1_C2M) is also
Lane 1 on the
AD9166 (Lane 1 of the Xilinx JESD204B IP)

Physical Lane 2 on the FMC connector (DP2_C2M) is also
Lane 2 on the
AD9166 (Lane 2 of the Xilinx JESD204B IP)

Physical Lane 3 on the FMC connector (DP3_C2M) is also
Lane 3 on the
AD9166 (Lane 3 of the Xilinx JESD204B IP)

Physical Lane 4 on the FMC connector (DP4_C2M) is
Lane 5 on the
AD9166 (Lane 5 of the Xilinx JESD204B IP)

Physical Lane 5 on the FMC connector (DP5_C2M) is
Lane 7 on the
AD9166 (Lane 7 of the Xilinx JESD204B IP)

Physical Lane 6 on the FMC connector (DP6_C2M) is also
Lane 6 on the
AD9166 (Lane 6 of the Xilinx JESD204B IP)

Physical Lane 7 on the FMC connector (DP7_C2M) is
Lane 4 on the
AD9166 (Lane 4 of the Xilinx JESD204B IP)
There is also input data pin polarity (positive and negative)
inversion between the transmitter and receiver on the evaluation
board to ease layout. The polarity can easily be inverted in the
Xilinx physical layer. Physical Lane 4 to Physical Lane 7
(DP4_C2M to DP7_C2M) on the FMC connector are inverted
(positive and negative swapped).
When bringing the JESD204B link up, the user can monitor
SYNCOUT± as indication of the link status.

If SYNCOUT± stays high, as indicated by a green check
mark next to
SYNC Status (see Figure 19), the link is
functional. However, if the signal spectrum appears to be
incorrect, it is possible that the physical lanes were not
mapped correctly.

If SYNCOUT± toggles between states, as indicated by a
yellow exclamation next to
SYNC Status
, the lane polarity
(positive and negative) may be inverted.

If SYNCOUT± remains low, as indicated by a red cross
next to
SYNC Status , there may be an issue with the
reference clocks arriving to the JESD204B transmitter, the
JESD204B receiver, or both.
Note that when selecting a
Lane Count
value of either 3 or 6,
Record Length must be set to a value that is a multiple of 3.
Otherwise, the spectrum does not output correctly. An example
is shown in Figure 19.
223
24-
019
Figure 19. Record Length When Lane Count = 3 or 6