Analog Devices AD9146-M5375-EBZ, Руководство пользователя

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AD9146-M5375-EBZ Evaluation Board User Guide UG-1630
Rev. 0 | Page 7 of 12
REFERENCE CLOCK
The AD9146 has an on-chip phase-locked loop (PLL) that uses
the REFCLKP and REFCLKN pins to supply the reference
clock. The AD9146-M5375-EBZ can supply the clock either
from the
AD9516-0 clock chip or from an additional external
signal generator by connecting to J14. Connecting the inner
pads to JP10 and JP15 selects the option to use the
AD9146 by
default, whereas soldering the outer pads chooses the external
option to drive from a sine source.
TRANSMIT ENABLE
The AD9146 has a transmit enable feature (active low) that
allows the user to control when the DACs transmit and when
the outputs are clamped. This feature can be used in the
DPGDownloader software or by forcing a voltage on the
TXENABLE pin via a test point. By default, the TXENABLE pin
is set by the
DPG3 . Connect JP1 horizontally, as shown in
Figure 6. To drive the TXENABLE pin manually, leave the
jumper unsoldered.