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Chapter 1
Getting Started
Figure 1-3.
PXIe_DSTAR and PXI Star Connectivity Diagram
PXI Local Bus
The PXI backplane local bus is a daisy-chained bus that connects each
peripheral slot with adjacent peripheral slots to the left and right, as shown
in Figure 1-4.
The backplane routes the full 13-line PXI Local Bus between adjacent
PXI slots (slots 6, 7, and 8) and PXI Local Bus 6 between all other slots.
Refer to Figure 1-4 for details. The left local bus 6 from slot 1 is not routed
anywhere and the right local bus signals from slot 8 are not routed
anywhere.
Local bus signals may range from high-speed TTL signals to analog signals
as high as 42 V.
PXI
S
t
a
r 0
PXI
S
t
a
r 2
PXI
S
t
a
r
3
PXI
S
t
a
r 5
PXI
S
t
a
r 6
PXI
S
t
a
r 1
PXI
S
t
a
r 4
P1
P2
P1
P2
P1
P2
P1
XP
3
XP4
P1
P2
XP
3
XP2
XP1
XP4
P1
XP
3
XP4
XP
3
TP2
XP4
S
lot 1:
S
y
s
tem Controller
S
lot
S
lot 2:
PXI P
er
ipher
a
l
S
lot
S
lot
3
: H
y
b
rid P
er
ipher
a
l
S
lot
S
lot 4:
S
y
s
tem Timing
S
lot
S
lot 5:
Hy
b
rid P
er
ipher
a
l
S
lot
S
lot 6:
PXI P
er
ipher
a
l
S
lot
S
lot 7:
PXI P
er
ipher
a
l
S
lot
S
lot
8
: PXI P
er
ipher
a
l
S
lot
PXIe_D
S
TAR0
PXIe_D
S
TAR9
PXIe_D
S
TAR
8
Manual
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