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Merlin DP PCI Motherboard User’s Guide
Chipset Setup
Chipset Setup options are displayed by choosing the Chipset icon from the
WINBIOS Setup main menu. All Chipset Setup options are described below.
PCI 2.1 Compliance
Set this option to Enabled to program the chipset to comply with the PCI
Version 2.1 specification. The settings are Enabled or Disabled. The Optimal
and Fail – Safe default settings are Disabled.
DRAM Speed (ns)
This option specifies the RAS access time (in nanoseconds) of the DRAM
used in the computer for system memory. The settings are 50 ns, 60 ns, or 70
ns. The Optimal and Fail – Safe default settings are 70 ns.
DRAM ECC Mode
This option sets the type of system memory checking. The settings are:
Setting Description
Disabled No error checking or error reporting is done. (Optimal and Fail – Safe default)
Level I Multibit errors are detected and reported as parity errors. Single – bit errors are
corrected by the chipset. Corrected bits of data from memory are not written back to
DRAM system memory. If Level I is selected, the J31 External SMI software jumper
on the motherboard is disabled.
Level II Multibit errors are detected and reported as parity errors. Single – bit errors are
corrected by the chipset and are written back to DRAM system memory.
If a soft (correctable) memory error occurs, writing the fixed data back to DRAM
system memory will resolve the problem. Most DRAM errors are soft errors. If a
hard (uncorrectable) error occurs, writing the fixed data back to DRAM system
memory does not solve the problem. In this case, the second time the error occurs in
the same location, a Parity Error is reported, indicating an uncorrectable error. If
Level II is selected, AMIBIOS automatically sets the Standard Power Management
option in Power Management Setup to Enabled to make sure that the System
Management Interface (SMI) is enabled. If you do not want to enable power
management, set the Advanced Power Management (APM) option to Disabled and
set all Power Management Setup timeout options to Disabled. To enable power
management, set Advanced Power Management (APM) to Enabled and set the
power management timeout options as desired.
The difference between Level I and Level II ECC is shown below. If a DRAM
SIMM has a single bit uncorrectable error, even writing fixed data to this bit
will not remove the error.
Setting then...
Level I the data error is fixed during the memory read cycle every time the bad bit is accessed
and the system continues to run, although every time the bad bit is read and
corrected, CPU cycles are wasted.
Level II the system tries to write the corrected data back to the bad bit in the DRAM SIMM.
Since the bad bit in the SIMM cannot be fixed, writing data to the bad bit has no
effect. The next time the error location is read, the chipset will once again find a bad
bit. The chipset generates a Parity Error, indicating an uncorrectable memory error.
Cont’d