AMD XILINX T2 Telco, Руководство пользователя

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Table 2: DDR4 PL Interface Pin Map (cont'd)
Pin Number Signal Name Description I/O
H20 PL_DDR4_1_DQS6# DDR4 Data Strobe 6 (N) Bidirectional
K21 PL_DDR4_1_DQS7 DDR4 Data Strobe 7 (P) Bidirectional
K22 PL_DDR4_1_DQS7# DDR4 Data Strobe 7 (N) Bidirectional
D23 PL_DDR4_1_DQS8 DDR4 Data Strobe 8 (P) Bidirectional
D24 PL_DDR4_1_DQS8# DDR4 Data Strobe 8 (N) Bidirectional
K12 PL_DDR4_1_ODT DDR4 On Die Termination O
K10 PL_DDR4_1_PAR DDR4 Parity O
E11 PL_DDR4_1_RAS# DDR4 Row Address Strobe O
F12 PL_DDR4_1_CAS# DDR4 Column Address Strobe O
K11 PL_DDR4_1_ACT# DDR4 Activate O
H8 PL_DDR4_1_CK DDR4 Clock (P) O
G8 PL_DDR4_1_CK# DDR4 Clock (N) O
K13 PL_DDR4_1_CKE DDR4 Clock Enable O
F11 PL_DDR4_1_CS# DDR4 Chip Select O
D14 PL_DDR4_1_WE# DDR4 Write Enable O
J10 PL_DDR4_1_ALERT# DDR4 Alert I
J14 PL_DDR4_1_RST# DDR4 Reset O
J13 PL_DDR4_1_TEN DDR4 Test Enable O
DDR4 PS Interface
The DDR4 PS interface is 40 bit (32 bits with 8-bit ECC) and operates at a maximum rate of
DDR2400.
Using the DDR4 PS Interface
• The DDR4 PS interface is supported with a dedicated IP block that must be enabled in the
design.
• The memory devices on the board are Micron MT40A512M16LY-062E:E (8 Gb 512Mx16).
• The maximum rate of DDR2400 is a Zynq ® Ult™ RFSoC -2E device limitation.
DDR4 PS Interface Pins
The following table summarizes the ZU48DR DDR4 PS interface pin map.
Chapter 3: Pin Mapping
UG1496 (v1.0) June 15, 2022 www.xilinx.com
T2 Telco Accelerator Card User Guide 15
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