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7 Series FPGAs and 
Zynq-7000 SoC XADC Dual 
12-Bit 1 MSPS 
Analog-to-Digital Converter

User Guide

UG480 (v1.11) June 13, 2022

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and partners feel welcome and included. To that end, we’re

removing non-inclusive language from our products and related

collateral. We’ve launched an internal initiative to remove

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Содержание XILINX 7 Series

Страница 1: ...we re removing non inclusive language from our products and related collateral We ve launched an internal initiative to remove language that could exclude people or reinforce historical biases includi...

Страница 2: ...XADC User Guide 2 UG480 v1 11 June 13 2022 www xilinx com...

Страница 3: ...Registers 34 DRP JTAG Interface 39 Zynq 7000 SoC Processing System PS to XADC Dedicated Interface 44 Chapter 4 XADC Operating Modes Single Channel Mode 45 Automatic Channel Sequencer 45 Sequencer Mod...

Страница 4: ...Analog Inputs 66 PC Board Design Guidelines 67 Appendix 7 Additional Resources and Legal Notices Xilinx Resources 78 Solution Centers 78 Documentation Navigator and Design Hubs 78 References 79 Revisi...

Страница 5: ...rich dual core Arm Cortex A9 based processing system PS and 28 nm Xilinx programmable logic PL in a single device This guide serves as a technical reference describing the 7 series FPGAs and Zynq 700...

Страница 6: ...ion This chapter contains only key information to allow a basic understanding of the XADC block With this introduction you can learn the pinout requirements and determine how to instantiate basic func...

Страница 7: ...the XADC is instantiated in a design using the block attributes Differences between Virtex 5 and Virtex 6 System Monitors For Virtex 5 and Virtex 6 FPGA System Monitor users the XADC functionality is...

Страница 8: ...reference for the ADCs To enable the on chip reference source the VREFP pin must be connected to ground as shown on the right of Figure 1 2 Where only basic on chip thermal and supply monitoring is r...

Страница 9: ...ected to GNDADC if an external reference is not supplied See Reference Inputs VREFP and VREFN page 64 for more information VREFN_0 Referencevoltage input This pin should be tied to the GND pin of an e...

Страница 10: ...cifications User Guide Ref 2 for more information The auxiliary analog inputs have a fixed package ball assignment and cannot be moved Auxiliary analog inputs are supported differently in Vivado tools...

Страница 11: ...ever if the XADC is not instantiated in a design the only way to access this information is through the JTAG test access port TAP To allow access to the status registers measurement results from the F...

Страница 12: ...instant on the ADC s inputs and is only used in event mode timing This input comes from the local clock distribution network in the FPGA logic Thus for the best control over the sampling instant delay...

Страница 13: ...tions to active High when the measurement data from the last channel in an automatic channel sequence is written to the status registers see Chapter 5 XADC Timing BUSY 2 Output ADC busy signal This si...

Страница 14: ...mulation of the XADC For more information see XADC Software Support page 69 Example Instantiation Instantiating the XADC involves connecting the required I O including analog inputs to the design and...

Страница 15: ...000 Sequencer Bipolar selection INIT_4E 16 h0000 Sequencer Acq time selection INIT_4F 16 h0000 Sequencer Acq time selection INIT_50 16 hb5ed Temp upper alarm trigger 85 C INIT_51 16 h5999 Vccint upper...

Страница 16: ...7FFh with 0 5V input and 800h with 0 5V input Temperature Sensor The temperature sensor has a transfer function given by Equation 1 2 Equation 1 2 For example ADC Code 2423 977h 25 C The temperature...

Страница 17: ...odes respectively All on chip sensors use the unipolar mode of operation for the ADC Users can optionally configure the external analog input channels to operate in unipolar or bipolar modes see Analo...

Страница 18: ...successive integer LSB values such as one LSB two LSBs and three LSBs etc The LSB size in volts is equal to 1V 212 or 1V 4096 244 V The analog input channels are differential in nature and require bo...

Страница 19: ...er function for bipolar mode operation The output coding of the ADC in bipolar mode is two s complement and is intended to indicate the sign of the input signal on VP relative to VN The designed code...

Страница 20: ...e voltage is equivalent to hundreds of LSBs thus inducing large measurement errors The differential sampling scheme samples both the signal and any common mode noise voltages at both analog inputs VP...

Страница 21: ...uxiliary analog inputs in an I O bank and use the remaining as digital I Os If there is a mixture of analog and digital I Os in a bank the I O bank must be powered by a supply required to meet the spe...

Страница 22: ...ion 2 3 The auxiliary analog channels such as VAUXP 15 0 and VAUXN 15 0 have a much larger RMUX resistance that is approximately equal to 10 k Equation 2 4 shows the minimum acquisition time in bipola...

Страница 23: ...types of signals the analog input must be configured to bipolar mode Bipolar mode is selected by writing to configuration register 0 see Control Registers All input voltages must be positive with resp...

Страница 24: ...K T Temperature K Kelvin C 273 15 q Charge on an electron 1 6 x 10 19 C The output voltage of this sensor is digitized by the ADC to produce a 12 bit digital output code ADC code Figure 2 9 illustrate...

Страница 25: ...hip sensors that allow a user to monitor the FPGA power supply voltages using the ADC The sensors sample and attenuate by a factor of three the power supply voltages VCCINT VCCAUX and VCCBRAM on the p...

Страница 26: ...power supply measurement results for VCCINT VCCAUX and VCCBRAM are stored in the status registers at DRP addresses 01h 02h and 06h respectively On Zynq 7000 SoC devices the measurements for VCCPINT VC...

Страница 27: ...FPGA logic port or the JTAG TAP Access is governed by an arbitrator see DRP Arbitration page 43 The DRP allows you to access up to 128 16 bit registers DADDR 6 0 00h to 7Fh The first 64 access locati...

Страница 28: ...60h Undefined 61h Undefined 62h Undefined 7Fh Undefined 7Dh Undefined 7Eh Sequence Reg 0 48h Sequence Reg 1 49h Sequence Reg 2 4Ah Sequence Reg 4 4Ch Sequence Reg 3 4Bh Sequence Reg 7 4Fh Sequence Re...

Страница 29: ...page 25 VCCINT 01h The result of the on chip VCCINT supply monitor measurement is stored at this location The data is MSB justified in the 16 bit register The 12 MSBs correspond to the supply sensor...

Страница 30: ...this register The 12 MSBs correspond to the ADC transfer function shown in Figure 2 10 page 26 The data is MSB justified in the 16 bit register The supply sensor is used when measuring VCCPAUX VCCO_DD...

Страница 31: ...nimum VCCPINT measurement recorded since power up or the last XADC reset VCCPAUX 1 min 2Dh MinimumVCCAUX measurementrecordedsincepower up or the last XADC reset VCCO_DDR 1 min 2Eh Minimum VCCO_DDR mea...

Страница 32: ...bits CAL0 3 in configuration register 1 41h see Table 3 5 page 36 BUSY transitions High for the duration of the entire calibration sequence conversion on channel 8 This calibration sequence is four t...

Страница 33: ...equivalent to 7 5 mV of offset in the supply measurement Gain Coefficients The ADC gain calibration coefficient stores the correction factor for any gain error in the ADCs The correction factor is st...

Страница 34: ...gisters Name Address Software Attribute Description Configuration register 0 40h INIT_40 These are XADC configuration registers see Configuration Registers 40h to 42h Configuration register 1 41h INIT...

Страница 35: ...fig Reg 1 DADDR 6 0 41h CD7 CD6 CD5 CD4 CD3 CD0 0 0 PD1 PD0 0 0 0 0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 CD2 CD1 Config Reg 2 DADDR 6 0 42h X17030 110817 Table 3 4 Con...

Страница 36: ...disables an alarm output DI9 to DI11 ALM4 to ALM6 These bits are used to disable individual alarm outputs for VCCPINT VCCPAUX and VCCO_DDR respectively A logic 1 disables an alarm output DI4 to DI7 CA...

Страница 37: ...annel 0 17 1 0 0 0 1 VAUXP 1 VAUXN 1 Auxiliary channel 1 18 31 VAUXP 2 15 VAUXN 2 15 Auxiliary channels 2 to 15 2 Notes 1 These channel selection options are used for XADC self check and calibration o...

Страница 38: ...sensor offset correction enable CAL3 Supply sensor offset and gain correction enable Table 3 11 Power Down Selection PD1 PD0 Description 0 0 Default All XADC blocks powered up 0 1 Not valid do not sel...

Страница 39: ...dary scan instruction 6 bit instruction 110111 called XADC_DRP added to 7 series FPGAs allows access to the DRP through the JTAG TAP All XADC JTAG instructions are 32 bits wide For more information on...

Страница 40: ...requested new read data see XADC DRP JTAG Read Operation This captured data is shifted out LSB first on DO as the new JTAG DRP command is shifted in The 16 LSBs of this 32 bit word contain the JTAG DR...

Страница 41: ...s several idle states at the end of the first DR scan operation allowing the arbitrator enough time to fetch the XADC DRP data As mentioned previously if the DCLK frequency is significantly faster tha...

Страница 42: ...le 3 13 It is also possible to enable the auxiliary analog input channel preconfiguration of the FPGA allowing external analog voltages on the PCB to be monitored using the JTAG TAP before configurati...

Страница 43: ...DRDY for the initial access becomes active and indicates the read write was successful If an interconnect access is in progress when a JTAG DRP transaction initiates the interconnect access is comple...

Страница 44: ...nterface and also reduce the overhead on the processor two 32 bit FIFOs have been implemented Up to 15 32 bit DRP JTAG command words see Table 3 13 can be loaded into the command FIFO The control logi...

Страница 45: ...here can be a significant overhead for the microprocessor or other controller To automate this task a function called the automatic channel sequencer is provided Automatic Channel Sequencer The automa...

Страница 46: ...t ADC mode see Simultaneous Sampling Mode and Independent ADC Mode respectively Table 4 1 Sequencer On Chip Channel Selection 48h Sequence Number 7 Series Zynq 7000 Bit ADC Channel Description 1 1 0 8...

Страница 47: ...e is Temperature VAUX 1 Temperature VAUX 1 Temperature VAUX 1 for each of the conversions where the temperature status register is updated The VAUX 1 status register is updated after the averaging of...

Страница 48: ...ic 1 in registers 4Eh and 4Fh the associated channel can have its settling time extended to 10 ADCCLK cycles The bit definitions which bits correspond to which external channels for these registers ar...

Страница 49: ...fault mode by writing zeros to SEQ0 and SEQ1 while updating these registers The XADC is automatically reset whenever SEQ3 to SEQ0 are written to The current status register contents are not reset at t...

Страница 50: ...In this mode the alarm outputs are active and you must correctly configure the alarm threshold Like default sequencer mode the averaging is fixed at 16 samples ADC B is available to be used with the e...

Страница 51: ...ode should be selected The XADC can then be returned to Independent ADC mode after EOS goes High at least once Sequencer Operation Channel selection for independent ADC mode is defined using sequencer...

Страница 52: ...cquisition on the next channel can start during the current conversion cycle An output bus called MUXADDR 4 0 allows the XADC to control an external multiplexer The address on this bus reflects the ch...

Страница 53: ...al multiplexer For example as shown in Figure 4 1 the dedicated analog input channel VP VN is used In this case channel 3 00011b should be written to CH4 to CH0 in Control Register 40h Any one of the...

Страница 54: ...ges state eight ADCCLK cycles after BUSY goes High X Ref Target Figure 4 2 Figure 4 2 External Multiplexer Mode for Simultaneous Sampling Mux VAUXP 0 VAUXN 0 VAUXP 8 VAUXN 8 MUXADDR 2 0 Mux FPGA VAUXP...

Страница 55: ...ment Temperature VCCINT VCCAUX VCCBRAM VCCPINT VCCPAUX or VCCO_DDR exceeds some user defined thresholds Only the values written to the status registers are used to generate alarms If averaging has bee...

Страница 56: ...the output alarms go active The alarms are reset when a subsequently measured value falls inside the threshold Table 4 8 Alarm Threshold Registers Control Register Description Alarm 50h Temperature up...

Страница 57: ...larm register 53h is 0000h including pre configuration To override this default condition the 12 MSBs of the OT upper register control register 53h must be set using the temperature sensor transfer fu...

Страница 58: ...the automatic shutdown feature can be disabled either by setting the OT signal within Config Reg 1 41h High or by adding the following constraint to the project XDC file set_property BITSTREAM CONFIG...

Страница 59: ...re 4 5 The black solid line shows the impact of the gain error and offset correction Because the ADC uncalibrated output reached full scale FFFh before the input reached 1V due to offset and gain erro...

Страница 60: ...tion register 0 see Control Registers Refer to the respective 7 series FPGAs data sheet for the latest XADC timing specifications The robust nature of the XADC ensures continued and correct operation...

Страница 61: ...nce on the acquisition see Analog Input Description Conversion Phase The conversion phase starts on the sampling edge next rising edge of DCLK at the end of the 4 or 10 ADCCLK cycles settling time The...

Страница 62: ...STCLK Therefore the acquisition time on a selected channel is also controlled by CONVST CONVSTCLK CONVST and CONVSTCLK are logically ORed within the XADC The T H starts to acquire the voltage on the n...

Страница 63: ...ta for this read operation is valid on the DO bus when DRDY goes high Thus DRDY should be used to capture the DO bus For a write operation the DWE signal is logic High and the DI bus and DRP address D...

Страница 64: ...es SOT 23 and SC70 The 1 25V reference should be placed as close as possible to the reference pins and connected directly to the VREFP input using the decoupling capacitors recommended in the referenc...

Страница 65: ...in PC Board Design Guidelines Notes relevant to Figure 6 1 1 Place the 100 nF capacitor as close as possible to the package balls see PC Board Design Guidelines page 67 The ferrite bead behaves like a...

Страница 66: ...ined by the sensor the output impedance of the driving circuitry or other external components Figure 6 3 illustrates a simple resistor divider network is used to monitor an external 2 5V supply rail i...

Страница 67: ...lting in ADC measurement corruption A discussion of aliasing in sampled systems is beyond the scope of this document A good data converter reference book can provide more information on this topic Ove...

Страница 68: ...rget Figure 6 4 Figure 6 4 Routing Channels to Center of Array Created by Staggering Vias X17044 110817 GNDADC VCCADC Note1 Note 2 Note 3 X17045 110817 X Ref Target Figure 6 5 Figure 6 5 Reference Inp...

Страница 69: ...field also allows the 100 nF decoupling on VREFP and VCCADC to be placed in the center of the array close to the package balls VREFP should be decoupled to VREFN and VCCADC to GNDADC near the package...

Страница 70: ...inimize any noise impacts This is especially true if the automatic alarm functions are used Averaging has been enabled for the on chip sensors in the instantiation shown below During simulation if a d...

Страница 71: ...drdy 8 h13 always posedge DCLK if RESET begin state init_read den_reg 2 h0 dwe_reg 2 h0 di_drp 16 h0000 end else case state init_read begin daddr 7 h40 den_reg 2 h2 performing read if busy 0 state rea...

Страница 72: ..._drp state read_reg02 end else begin den_reg 1 b0 den_reg 1 dwe_reg 1 b0 dwe_reg 1 state state end read_reg02 begin daddr 7 h02 den_reg 2 h2 performing read state reg02_waitdrdy end reg02_waitdrdy if...

Страница 73: ...gin MEASURED_AUX1 do_drp state read_reg12 end else begin den_reg 1 b0 den_reg 1 dwe_reg 1 b0 dwe_reg 1 state state end read_reg12 begin daddr 7 h12 den_reg 2 h2 performing read state reg12_waitdrdy en...

Страница 74: ...upper alarm limit 1 89V INIT_53 16 h0000 OT upper alarm limit 125 C using automatic shutdown see Thermal Management INIT_54 16 ha93a Temp lower alarm reset 60 C INIT_55 16 h5111 Vccint lower alarm lim...

Страница 75: ...PICE simulators or even equipment such as oscilloscopes export comma separated value CSV formats which are manipulated in a spreadsheet to generate an analog stimulus file for simulation All time stam...

Страница 76: ...w the test bench carries out a DRP write to register 40h Configuration Register 0 to set the AVG1 and AVG0 bits to 00 see Figure 6 7 This disables the averaging functionality for simulation X Ref Targ...

Страница 77: ...how the VCCAUX_ALARM output goes high during the second pass through the sequence Figure 6 6 The alarm goes active at the end of the conversion on the VCCAUX channel when the result is loaded in the...

Страница 78: ...ts videos and support resources which you can filter and search to find information To open the Xilinx Documentation Navigator DocNav From the Vivado IDE select Help Documentation and Tutorials On Win...

Страница 79: ...er Guide 4 UG585 Zynq 7000 All Programmable SoC Technical Reference Manual 5 PG091 XADC Wizard LogiCORE IP Product Guide for Vivado Design Suite 6 XAPP554 XADC Layout Guidelines Application Note 7 XAP...

Страница 80: ...ootnotes were added to support 7 series and Zynq device pin packages A note about application guidelines was added after Table 1 1 Information about auxiliary analog channels was added to the External...

Страница 81: ...ter The Dynamic Reconfiguration Port DRP Timing section was added Removed Table 5 1 XADC Timing Information In Reference Inputs VREFP and VREFN added Noise on the reference voltage also adds noise to...

Страница 82: ...WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE SAFETY APPLICATION UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE...

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