AMD RS690M, Техническое справочное руководство

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© 2008 Advanced Micro Devices, Inc. 41978 AMD RS690M Databook 3.06
Proprietary 4-1
Chapter 4
Timing Specifications
4.1 CPU HyperTransport ™ Bus Timing
For HyperTransport bus timing information, please refer to CPU specifications.
4.2 HyperTransport ™ Reference Clock Timing Parameters
4.3 PCI Express
®
Differential Clock AC Specifications
4.4 Side-port Memory Timing (RS690T Only)
The RS690T’s side-port memory DDR2 interface complies with all the timing requirements given in the JESD79-2B
specification. Please refer to the JEDEC standard for any timing details.
4.4.1 Read Cycle DQ/DQS Delay
During a memory read cycle, there is a DLL inside the RS690T that can delay each DQS signal with respect to its byte of
the DQ valid window. This delay ensures adequate setup and hold time to capture the memory data. This DLL delay is
programmable through the following registers:
MCA_DLL_SLAVE_RD_0. MCA_DLL_ADJ_DQSR_0 <NBMCIND : 0xE0[7:0]>
MCA_DLL_SLAVE_RD_1. MCA_DLL_ADJ_DQSR_1 <NBMCIND : 0xE1[7:0]>
Table 4-1 HTREFCLK Pad (66.66MHz) Timing Parameters
Symbol Parameter Min Typ Max Unit Comment
TIP REFCLK Period – 15 – ns
Time intervals measured at 50%
VDDCK threshold point
FIP REFCLK Frequency – 66.66 – MHz
FIP is the reciprocal of TIP.
TIH REFCLK High Time 2 – – ns –
TIL REFCLK Low Time 2 – – ns –
TIR REFCLK Rise Time – – 1.5 ns –
TIF REFCLK Fall Time – – 1.5 ns –
TIJCC REFCLK Cycle-to-Cycle Jitter Requirement – – 300 ps –
TIJLT
REFCLK Long Term Jitter Requirement
(1
µ
s after scope trigger)
– – 1 ns –
Table 4-2 PCI Express
®
Differential Clock (GFX_CLK, SB_CLK) AC Characteristics
Parameter Minimum Maximum Unit
Absolute Minimum Differential Clock Period 9.872 – ns
Rise Time 175 700 ps
Fall time 175 700 ps
Rise/Fall Matching – 20 %
Cycle-to-Cycle Jitter – 125 ps
Duty Cycle 45 55 %