AMD Elan SC520, Руководство пользователя

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System Address Mapping
Élan™SC520 Microcontroller User’s Manual 4-9
4.3.3.3 GP Bus Memory Space
GP bus memory space is enabled only through PAR registers and is accessible only by
the CPU. There are eight chip selects that can be selected by the PAR registers. Note that
the PAR registers do not allow any attributes to be defined in GP bus memory space regions,
and GP bus memory space is always noncacheable.
The PAR registers are used to select GP bus space and the specific chip select, but separate
configuration registers within the GP bus controller block must be programmed to control
the width of the data bus and the timing of the bus. There is no restriction on the mapping
of memory address space to GP bus chip selects. For example, if a noncontiguous memory
region is required for a specific chip select, then multiple PAR registers can be programmed
with the same chip select as the target, but with different address ranges.
Positive address decoding is also supported on the GP bus for devices that perform their
own address decoding and therefore do not require a chip select to be generated by the
ÉlanSC520 microcontroller. This is accomplished simply by not choosing the corresponding
chip select in the pin multiplexing registers when the PAR register is set up (see step 3 in
“Programming External Memory, Buses, and Chip Selects” on page 4-4). The address and
control signals are still generated on the GP bus.
PCI bus masters are not permitted to access the GP bus in an ÉlanSC520 microcontroller
system. If a PCI bus master generates an address in normal SDRAM space that is claimed
by the ÉlanSC520 microcontroller, but the region has been redirected to the GP bus via a
PAR register, the cycle will still be sent to SDRAM and will be write-protected, regardless
of the cycle type, and the resultant data will be discarded.
4.3.3.4 PCI Bus Memory Space
The ÉlanSC520 microcontroller’s address decoding logic automatically defaults all memory
space above configured SDRAM to the PCI bus, with the exception of the 4-Kbyte memory-
mapped configuration space and the 64-Kbyte boot space. All CPU memory space
accesses in this address region are redirected to the PCI bus, and the ÉlanSC520
microcontroller does not claim accesses in this address region that are generated by PCI
bus masters. The GP bus DMA controller cannot access this region.
The CPU can allocate space within the lower 1 Gbyte for GP bus or ROM, overlaying and
effectively eliminating parts of this PCI bus region. For example, a ROM device could be
mapped in memory between the top of SDRAM and 1 Gbyte, a region that would normally
default to PCI bus. In this case, only this particular region would be redirected to ROM, but
the remaining region within the 4-Gbyte space would continue to be directed to the PCI bus.
Some system applications may require a region below the top of SDRAM to be redirected
to the PCI bus. An example of this is a PCI bus video card mapped to the 000A0000h-
000BFFFFh region in a PC/AT application. In this case, a PAR register must be used to
redirect the address from the CPU to the PCI bus instead of the SDRAM. Note that only
PAR 0 or PAR 1 can be used to select PCI as a target.
4.3.3.5 Memory-Mapped Configuration Region (MMCR) Registers Space
All integrated peripherals and configuration registers in the ÉlanSC520 microcontroller that
are not defined as PCI bus configuration space, PC/AT peripheral configuration registers,
or the Configuration Base Address (CBAR) register are memory-mapped in the ÉlanSC520
microcontroller. These registers are accessed in a 4-Kbyte region near the top of CPU
address space at location FFFEF000h after reset, but can be additionally aliased to any
4-Kbyte boundary within the first 1-Gbyte of memory space (between 00000000h and
3FFFFFFFh) by performing an I/O write to the Configuration Base Address (CBAR) register.