AMD Elan SC520, Руководство пользователя

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System Test and Debugging
24-6 Élan™SC520 Microcontroller User’s Manual
configuration of the ROM array must be known, because the ROM data bus can be
connected to either the SDRAM interface data pins (MD31
± MD0), or the GP bus interface
data pins (GPD15 ± GP0). Also, the timing of the ROM cycle will vary, depending on the
device that has been connected to each of the ROM chip selects and the programming of
the ROM controller configuration registers. The following pins can be monitored to trace
transactions on the ROM interface:
■
CF_ROM_GPCS if it is necessary to identify code fetches
■ GPA25 ± GPA0 ROM non-multiplexed address bus
■
GPD15
±
GPD0 ROM data bus, or MD31
±
MD0 SDRAM data bus, depending on the
programming of the ROM controller configuration registers
■
ROM chip selects BOOTCS, and optionally ROMCS1 and ROMCS2
■ ROMRD, FLASHWR control signals
See Chapter 12, “ROM/Flash Controller”, for further details of ROM interface signals and
timing to determine the appropriate time when the address and data pins are valid.
24.4.1.6 Tracing Transactions on the GP Bus Interface
Capturing transactions on the GP bus interface requires only the CF_ROM_GPCS signal
if it is desired to differentiate code fetches from memory read cycles. However, some further
signal qualification is required to filter out GP-DMA transactions from Am5
x
86 CPU cycles.
PCI bus masters are not permitted to initiate cycles on the GP bus. The signals required
to trace cycles on the GP bus will vary depending on the type of slave devices connected
externally.
Note that due to performance limitations of the GP bus, it is highly recommended that code
execution from this bus be avoided.
The GPAEN signal must be monitored by the GP bus devices when GP-DMA initiators are
connected on the GP bus to prevent address decoding during GP-DMA cycles. GP bus
control signals asserted when the GPAEN signal is active (High) are controlling a read or
write of a GP-DMA initiator, and the address on the GPA25
± GPA0 pins are invalid. GPAEN
is also driven active during internally echoed cycles to prevent address decoding by GP
bus devices.
Since the GP bus supports several different cycle types, dynamic bus sizing, and timing
control, there are numerous signals that may be required for adequate tracing of GP bus
transactions. The following list summarizes the various signals that should be considered
for such tracing.
■ CF_ROM_GPCS if it is necessary to identify code fetches
■
GPA25 ± GPA0 non-multiplexed address bus
■ GPD7 ± GPD0 data bus for 8-bit cycles, or GPD15 ± GPD0 for 16-bit cycles
■
GP bus chip selects, multiplexed on ROMCS1 or ROMCS2, or PIO pins
■ GPALE, GPIORD/GPMEMRD, GPIOWR/GPMEMWR, GPAEN control signals
■
GPRDY signal for devices that dynamically stretch GP bus cycles
■ GPIOCS16 and GPMEMCS16 for devices that dynamically identify the bus width of the
target device’s cycle
See Chapter 13, “General-Purpose Bus Controller”, for details of cycle timing.