AMD Elan SC520, Руководство пользователя

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General-Purpose Bus Controller
13-22 Élan™SC520 Microcontroller User’s Manual
13.6 INITIALIZATION
The GP bus controller is reset by a system reset. The internal GP bus is enabled, as are
holes in the lower 1-Kbyte of I/O space; however, no chip selects are enabled. The external
GP bus is disabled until the Programmable Address Region (PAR) registers are initialized.
GP bus reset can be generated via a system reset or software write. Writing a 1 to the
GP_RST bit in the Reset Configuration (RESCFG) register (MMCR offset D72h) asserts
the GPRESET pin. Clearing this bit to 0 deasserts the GPRESET pin. The GPRESET pin
is only used for external GP bus peripherals. When this signal is asserted, all devices
connected to the GP bus should re-initialize to their reset state.
To enable the GP bus controller:
1. Configure the address decoding region for each chip select in the PAR registers.
2. Configure the external chip select pins in the Chip Select Pin Function Select (CSPFS)
register (MMCR offset C24h).
3. Configure the external GP bus timing in the programmable interface timing registers, as
described in this chapter.
4. Configure the data width of each chip select in the GP Chip Select Data Width
(GPCSDW) register (MMCR offset C01h).
5. Optionally, program the GP Chip Select Qualification (GPCSQUAL) register (MMCR
offset C02h) to qualify the chip select with the read or write strobes, if needed.
6. Optionally, program the GP Echo Mode (GPECHO) register (MMCR offset C00h) to
enable the GP bus echo mode, if needed.