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Write Buffer and Read Buffer
11-10 Élan™SC520 Microcontroller User’s Manual
The SDRAM controller’s arbiter supports a write buffer park feature, such that after the
write buffer’s watermark is reached and requests SDRAM service, the SDRAM controller’s
arbiter continues to grant the write buffer SDRAM service, until either a master read cycle
is requested to SDRAM or a SDRAM refresh occurs. After the write buffer’s grant is
removed, the write buffer’s watermark will need to be exceeded prior to the write buffer
requesting SDRAM service again. This park feature allows the write buffer to utilize SDRAM
access until a higher priority master read or an SDRAM refresh cycle is requested.
11.5.2 Read Buffer and the Read-Ahead Feature
The SDRAM controller contains eight 4-byte read data buffers. Combined, these buffers
make up the read buffer and are designed to hold two cache lines of data returned from
SDRAM. The read buffer is designed to increase SDRAM read performance by storing
previously read data from SDRAM and supplying this data in zero wait states to a requesting
master.
The SDRAM controller always fetches an entire cache line of data from SDRAM and stores
it in the read buffer, independently of the amount of data requested during the master
access. For example, during a read request from a non-bursting master (i.e., single
doubleword request), the SDRAM controller fetches the entire cache line of data from
SDRAM and stores it in the read buffer. When the read-ahead feature of the read buffer is
enabled and the master read access is a burst of two or more doublewords, not only is the
requested cache line (i.e., the demanded line) of data retrieved from SDRAM, but also the
cache line following it.
A demand fetch implies that the SDRAM controller will be servicing the read request from
the master as it occurs. When the read-ahead feature is enabled, a read-ahead prefetch
only occurs for master demand burst requests of two or more doublewords. The read-ahead
feature takes advantage of the linear forward-fetch nature of the Am5
x
86 CPU and PCI
bursts. GP-DMA transfers are non-burst, and thus do not result in a prefetch. However,
GP-DMA transfers can utilize the remainder of the cache line, since all read accesses result
in a cache line access to SDRAM.
The read buffer provides storage for two cache lines of read data and cannot be disabled.
The read-ahead feature of the read buffer can be disabled.
11.5.2.1 Read-Ahead Feature Disabled
When the read-ahead feature is disabled, the prefetch feature of the SDRAM controller is
disabled. All master read requests that occur to SDRAM are demand fetches and always
result in an entire cache line of data being read from SDRAM. Even when the read-ahead
feature is disabled, both cache lines of storage of the read buffer are still utilized and contain
the last two demand cache line fetches.
11.5.2.2 Read-Ahead Feature Enabled
When the read-ahead feature is enabled, following cache line prefetches from SDRAM will
occur when the read access is a burst of two or more doublewords. The prefetched cache
line always follows the demanded cache line. Should an access result in a read buffer hit,
the read-ahead logic will request the cache line following the access that is currently being
supplied from the read buffer.
The read buffer is organized as two cache lines of data and an associated address tag. On
every read cycle these tags are compared to the read address being requested. If the
compare results in a hit, this data is supplied to the requesting master in zero wait states.
If, during this hit, the
next cache line of data does not already exist in the read buffer, the
prefetch logic will request it from SDRAM. Should a request result in a read buffer miss,
the demanded read cycle request is satisfied by SDRAM, and the prefetch logic starts a