PCI Bus Host Bridge
9-22
Élan™SC520 Microcontroller User’s Manual
register (MMCR offset 60h). The T_PURGE_RD_ENB bit must not be changed except
during PCI bus initialization after a system or programmable reset.
■
Memory-read and memory-read-line commands generate a purge when the write
address is within the same cache line as the prefetched data. Note that the addresses
do not necessarily overlap in this case. For example, a memory-read command to 5008h
will prefetch 5008h and 500Ch. A memory-write command to 5000h will then cause a
purge because it is in the same cache line, even though the addresses do not overlap.
■
Memory-read-multiple commands generate a purge if the write is in the same 64-
doubleword region as the prefetched data. In this case, exact addresses are compared.
Note that a write to the same 64-doubleword region causes a purge even if the prefetch
is not complete. If, for example, the host bridge is prefetching the 32nd doubleword on
the Am5
x
86 CPU bus, and a write comes into the 53rd doubleword (or any number
greater than 32 and less than 64, in this case), this write will cause a purge.
9.5.4.9
PCI Host Bridge Target Bus Cycles
This section describes in detail the cycles generated by an external PCI bus master for
which the ÉlanSC520 microcontroller PCI host bridge responds, and includes both the PCI
bus and the internal Am5
x
86 CPU bus. The PCI host bridge forwards cycles that are
destined to SDRAM from the PCI bus to the Am5
x
86 CPU bus.
The examples shown apply primarily to concurrent arbitration mode; there are a few
differences when operating in nonconcurrent arbitration mode. See Chapter 8, “System
Arbitration”, for further details on the arbitration modes.
Note that these are example cases only, and not all cases are shown. The diagrams are
functionally representative in nature, and should not be used to infer detailed timing
information. Note also that the synchronization between the CPU and PCI clock domains
is not shown in detail.
9.5.4.9.1
External PCI Bus Master Posted Write to SDRAM
Figure 9-14 shows an external PCI bus master writing seven doublewords to the
ÉlanSC520 microcontroller’s SDRAM. The first group of signals are the PCI bus signals,
and the second group are internal signals.
Содержание Elan SC520
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Страница 78: ...System Initialization 3 22 lan SC520 Microcontroller User s Manual...
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Страница 288: ...GP Bus DMA Controller 14 22 lan SC520 Microcontroller User s Manual...
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Страница 328: ...Software Timer 18 4 lan SC520 Microcontroller User s Manual...
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Страница 360: ...UART Serial Ports 21 14 lan SC520 Microcontroller User s Manual...
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