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Preliminary Information

AMD Athlon XP

Processor Model 10

Data Sheet

Publication #

26237

Rev.

Issue Date:

May 2003

Содержание Athlon XP 10

Страница 1: ...Preliminary Information AMD Athlon XP Processor Model 10 Data Sheet Publication 26237 Rev C Issue Date May 2003 TM...

Страница 2: ...s to specifications and prod uct descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publ...

Страница 3: ...3 Front Side Bus AMD Athlon XP Processor Model 10 Specifications 21 6 1 Electrical and Thermal Specifications for the Advanced 333 FSB AMD Athlon XP Processor Model 10 21 6 2 Advanced 333 FSB AMD Athl...

Страница 4: ...C Pins AC and DC Characteristics 41 9 Signal and Power Up Requirements 43 9 1 Power Up Requirements 43 Signal Sequence and Timing Description 43 Clock Multiplier Selection FID 3 0 46 9 2 Processor War...

Страница 5: ...76 PWROK Pin 76 SADDIN 1 0 and SADDOUT 1 0 Pins 77 Scan Pins 77 SMI Pin 77 STPCLK Pin 77 SYSCLK and SYSCLK 77 THERMDA and THERMDC Pins 77 VCCA Pin 77 VID 4 0 Pins 77 VREFSYS Pin 78 ZN and ZP Pins 78...

Страница 6: ...vi Table of Contents AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 7: ...7 Processor Connect State Diagram 17 Figure 8 SYSCLK Waveform 22 Figure 9 SYSCLK Waveform 26 Figure 10 VCC_CORE Voltage Waveform 33 Figure 11 SYSCLK and SYSCLK Differential Clock Signals 35 Figure 12...

Страница 8: ...viii List of Figures AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 9: ...able 8 Advanced 400 FSB AMD Athlon System Bus DC Characteristics 28 Table 9 Interface Signal Groupings 29 Table 10 VID 4 0 DC Characteristics 30 Table 11 FID 3 0 DC Characteristics 31 Table 12 VCCA AC...

Страница 10: ...D 3 0 Clock Multiplier Encodings 74 Table 26 Front Side Bus Sense Truth Table 75 Table 27 VID 4 0 Code to Voltage Definition 78 Table 28 Constants and Variables for the Ideal Diode Equation 81 Table 2...

Страница 11: ...le 6 Advanced 400 FSB SYSCLK and SYSCLK AC Characteristics on page 26 Figure 9 SYSCLK Waveform on page 26 Table 7 Advanced 400 FSB AMD Athlon System Bus AC Characteristics on page 27 and Table 8 Advan...

Страница 12: ...xii Revision History AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 13: ...capability digital content creation digital photo editing digital video image compression video encoding for streaming over the Internet soft DVD commercial 3D modeling workstation class computer aide...

Страница 14: ...Professional technology implemented in the AMD Athlon XP processor model 10 includes new integer multimedia instructions and software directed data movement instructions for optimizing such applicati...

Страница 15: ...rocessor model 10 is compatible with motherboards based on Socket A Figure 1 shows a typical AMD Athlon XP processor model 10 system block diagram Figure 1 Typical AMD Athlon XP Processor Model 10 Sys...

Страница 16: ...4 Overview Chapter 1 AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 17: ...nce controlled push pull low voltage swing signaling technology contained within the Socket A socket For more information see AMD Athlon System Bus Signals on page 6 Chapter 11 Pin Descriptions on pag...

Страница 18: ...nce of the motherboard by two external resistors connected to the ZN and ZP pins See ZN and ZP Pins on page 78 for more information 2 4 AMD Athlon System Bus Signals The AMD Athlon system bus is a clo...

Страница 19: ...ram SDATA 63 0 SDATAINCLK 3 0 SDATAOUTCLK 3 0 Data SADDIN 14 2 SADDINCLK Probe SysCMD SADDOUT 14 2 SADDOUTCLK VID 4 0 FID 3 0 A20M CLKFWDRST CONNECT COREFB COREFB FERR IGNNE INIT INTR NMI PROCRDY PWRO...

Страница 20: ...8 Logic Symbol Diagram Chapter 3 AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 21: ...agement states of the processor The figure includes the ACPI Cx naming convention for these states Figure 3 AMD Athlon XP Processor Model 10 Power Management States C1 Halt C0 Working4 Execute HLT SMI...

Страница 22: ...initiate a system bus connect if it is disconnected then issue a Stop Grant special cycle When STPCLK is deasserted the processor will exit the Stop Grant state and re enter the Halt state The proces...

Страница 23: ...cognized If RESET is sampled asserted during the Stop Grant state the processor exits the Stop Grant state and the reset process begins There are two mechanisms for asserting STPCLK hardware and softw...

Страница 24: ...robe state Halt or Stop Grant state When probe activity is completed the processor only returns to a low power state after the Northbridge disconnects the AMD Athlon system bus again 4 2 Connect and D...

Страница 25: ...he Stop Grant special cycle to the Southbridge for systems that connect to the Southbridge with HyperTransport technology This note applies to current chipset implementation alternate chipset implemen...

Страница 26: ...rant state 2 When the processor recognizes STPCLK asserted it enters the Stop Grant state and then issues a Stop Grant special cycle 3 When the special cycle is received by the Northbridge it deassert...

Страница 27: ...oves the processor from the Stop Grant state and connects it to the system bus 1 The Southbridge deasserts STPCLK informing the processor of a wake event 2 When the processor recognizes STPCLK deasser...

Страница 28: ...special cycle from the processor 4 No probes are pending 5 PROCRDY is deasserted 6 A probe needs service 7 PROCRDY is asserted 8 Three SYSCLK periods after CLKFWDRST is deasserted Although reconnecte...

Страница 29: ...ST is deasserted by the Northbridge 6 Forward clocks start three SYSCLK periods after CLKFWDRST is deasserted Action A CLKFWDRST is asserted by the Northbridge B Issue a Connect special cycle C Return...

Страница 30: ...Clock Control The processor implements a Clock Control CLK_Ctl MSR address C001_001Bh that determines the internal clock divisor when the AMD Athlon system bus is disconnected Refer to the AMD Athlon...

Страница 31: ...rmation about the processor vendor type name etc and its capabilities Software can make use of this information to accurately tune the system for maximum performance and benefit to users For informati...

Страница 32: ...20 CPUID Support Chapter 5 AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 33: ...000 45 0 A 35 4 A 74 3 W 58 4 W Notes 1 See Figure 3 AMD Athlon XP Processor Model 10 Power Management States on page 9 2 The maximum Stop Grant currents are absolute worst case currents for parts tha...

Страница 34: ...me 1 0 ns t3 Low Time 1 0 ns t4 Fall Time 2 ns t5 Rise Time 2 ns Period Stability 300 ps Notes 1 The AMD Athlon system bus operates at twice this clock frequency 2 Circuitry driving the AMD Athlon sys...

Страница 35: ...Input Data Setup Time 300 ps 3 THD Input Data Hold Time 300 ps 3 CIN Capacitance on input clocks 4 25 pF COUT Capacitance on output clocks 4 12 pF Sync TVAL RSTCLK to Output Valid 800 2000 ps 4 5 TSU...

Страница 36: ...VREF Nominal 100 A IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN VREF Nominal 100 A VIH Input High Voltage VREF 200 VCC_CORE 500 mV VIL Input Low Voltage 500 VREF 200 mV ILEAK_P Tristate Leakage Pul...

Страница 37: ...36 6 A 76 8 W 60 4 W Notes 1 See Figure 3 AMD Athlon XP Processor Model 10 Power Management States on page 9 2 The maximum Stop Grant currents are absolute worst case currents for parts that may yiel...

Страница 38: ...1 0 ns t3 Low Time 1 0 ns t4 Fall Time 1 5 ns t5 Rise Time 1 5 ns Period Stability 300 ps Notes 1 The AMD Athlon system bus operates at twice this clock frequency 2 Circuitry driving the AMD Athlon s...

Страница 39: ...Input Data Setup Time 300 ps 3 THD Input Data Hold Time 300 ps 3 CIN Capacitance on input clocks 4 25 pF COUT Capacitance on output clocks 4 12 pF Sync TVAL RSTCLK to Output Valid 800 2000 ps 4 5 TSU...

Страница 40: ...VREF Nominal 100 A IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN VREF Nominal 100 A VIH Input High Voltage VREF 150 VCC_CORE 500 mV VIL Input Low Voltage 500 VREF 150 mV ILEAK_P Tristate Leakage Pul...

Страница 41: ...ontained in each group Table 9 Interface Signal Groupings Signal Group Signals Notes Power VID 4 0 VCCA VCC_CORE COREFB COREFB See Voltage Identification VID 4 0 on page 30 VID 4 0 Pins on page 77 VCC...

Страница 42: ...e 77 INIT Pin on page 75 A20M Pin on page 72 FERR Pin on page 73 IGNNE Pin on page 75 STPCLK Pin on page 77 and FLUSH Pin on page 75 JTAG TMS TCK TRST TDI TDO See General AC and DC Characteristics on...

Страница 43: ...0 DC Characteristics Parameter Description Min Max IOL Output Current Low 6 mA VOH Output High Voltage 2 625 V 1 VOH VCC_CORE 1 60 V 2 Note 1 The FID pins must not be pulled above 2 625 V which is equ...

Страница 44: ...d DC Characteristics Symbol Parameter Limit in Working State Units VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM 50 mV VCC_CORE_DC_MIN Maximum static voltage below VCC_CORE_NOM 50 mV VCC_C...

Страница 45: ...aveform response to perturbation The tMIN_AC negative AC transient excursion time and tMAX_AC positive AC transient excursion time represent the maximum allowable time below or above the DC tolerance...

Страница 46: ...s can adversely affect long term reliability or result in functional damage Table 14 lists the maximum absolute ratings of operation for the AMD Athlon XP processor model 10 Table 14 Absolute Ratings...

Страница 47: ...CLK and SYSCLK signals Figure 11 SYSCLK and SYSCLK Differential Clock Signals Table 15 SYSCLK and SYSCLK DC Characteristics Symbol Description Min Max Units VThreshold DC Crossing before transition is...

Страница 48: ...ltage range 2 Values specified at nominal VCC_CORE Scale parameters between VCC_CORE minimum and VCC_CORE maximum 3 IOL and IOH are measured at VOL maximum and VOH minimum respectively 4 Synchronous i...

Страница 49: ...are specified with respect to RSTCLK and RSTCK at the pins 5 These are aggregate numbers 6 Edge rates indicate the range over which inputs were characterized 7 In asynchronous operation the signal mus...

Страница 50: ...utomated test equipment ATE to test for validity on open drain pins Refer to Table 16 General AC and DC Characteristics on page 36 for timing requirements Figure 12 General ATE Open Drain Test Circuit...

Страница 51: ...de Calculations on page 77 Thermal Protection Characterization The following section describes parameters relating to thermal protection The implementation of thermal control circuitry to control proc...

Страница 52: ...AMD Athlon Processor Based Motherboard Design Guide order 24363 AMD Thermal Mechanical and Chassis Cooling Design Guide order 23794 See http www amd com for more information about thermal solutions Ta...

Страница 53: ...VCC_CORE VCC_CORE_MAX VOH VCC_CORE 1 60 V V 3 VOL Output Low Voltage 300 400 mV ILEAK_P Tristate Leakage Pullup VIN VSS Ground 1 mA ILEAK_N Tristate Leakage Pulldown VIN 2 5 V 1 mA IOL Output Low Curr...

Страница 54: ...42 Electrical Data Chapter 8 AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 55: ...and Timing Description Figure 13 shows the relationship between key signals in the system during a power up sequence This figure details the requirements of the processor Figure 13 Signal Relationship...

Страница 56: ...conds from the 3 3 V supply being within specification This delay ensures that the system clock SYSCLK SYSCLK is operating within specification when PWROK is asserted The processor core voltage VCC_CO...

Страница 57: ...eet the timing requirements as defined in Table 12 General AC and DC Characteristics on page 34 The processor should not switch between the ring oscillator and the PLL after the initial assertion of P...

Страница 58: ...0 code The SIP is sent to the processor using the SIP protocol This protocol uses the PROCRDY CONNECT and CLKFWDRST signals that are synchronous to SYSCLK For more information about FID 3 0 see FID 3...

Страница 59: ...from the die to an approved heat sink Any heat sink design should avoid loads on corners and edges of die The OPGA package has compliant pads that serve to bring surfaces in planar contact Tool assist...

Страница 60: ...Symbol Minimum Dimension1 Maximum Dimension1 Letter or Symbol Minimum Dimension1 Maximum Dimension1 D E 49 27 49 78 E9 1 66 1 96 D1 E1 45 72 BSC G H 4 50 D2 7 42 REF A 1 942 REF D3 3 30 3 60 A1 1 00 1...

Страница 61: ...Chapter 10 Mechanical Data 49 26237C May 2003 AMD Athlon XP Processor Model 10 Data Sheet Preliminary Information Figure 14 AMD Athlon XP Processor Model 10 Part Number 27488 OPGA Package Diagram...

Страница 62: ...ter or Symbol Minimum Dimension1 Maximum Dimension1 Letter or Symbol Minimum Dimension1 Maximum Dimension1 D E 49 27 49 78 G H 4 50 D1 E1 45 72 BSC A 1 917 REF D2 7 42 REF A1 0 977 1 177 D3 3 30 3 60...

Страница 63: ...Chapter 10 Mechanical Data 51 26237C May 2003 AMD Athlon XP Processor Model 10 Data Sheet Preliminary Information Figure 15 AMD Athlon XP Processor Model 10 Part Number 27493 OPGA Package Diagram...

Страница 64: ...52 Mechanical Data Chapter 10 AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 65: ...ations and a cross referenced listing of pin locations to signal names 11 1 Pin Diagram and Pin Name Abbreviations Figure 16 on page 54 shows the staggered Pin Grid Array PGA for the AMD Athlon XP pro...

Страница 66: ...C VSS VSS VSS VSS R S SCNCK1 SCNINV SCNCK2 THDA NC SD 7 SD 15 SD 6 S T VSS VSS VSS VSS VCC VCC VCC VCC T U TDI TRST TDO THDC NC SD 5 SD 4 NC U V VCC VCC VCC VCC VSS VSS VSS VSS V W FID 0 FID 1 VREF_S...

Страница 67: ...EY NC CLKIN CLKIN 17 18 VSS VSS VSS VSS VCC VCC VCC VCC 18 19 NC SD 59 SD 58 NC NC NC RCLK RCLK 19 20 VCC VCC VCC VCC VSS VSS VSS VSS 20 21 SD 57 SD 56 SD 36 NC NC CLKFR K7CO K7CO 21 22 VSS VSS VSS VS...

Страница 68: ...AG1 FID 0 W1 FID 1 W3 FID 2 Y1 FID 3 Y3 FLUSH AL3 FSB0 FSB_Sense 0 AG31 FSB1 FSB_Sense 1 AH30 IGNNE AJ1 INIT AJ3 INTR AL1 K7CO K7CLKOUT AL21 K7CO K7CLKOUT AN21 KEY G7 KEY G9 KEY G15 KEY G17 KEY G23 K...

Страница 69: ...me Abbreviations continued Abbreviation Full Name Pin NC AJ19 NC AJ27 NC AK8 NC AL7 NC AL9 NC AL11 NC AL25 NC AL27 NC AM8 NC AN7 NC AN9 NC AN11 NC AN25 NC AN27 NMI AN3 PICCLK N1 PICD 0 PICD 0 N3 PICD...

Страница 70: ...SCANCLK2 S5 SCNINV SCANINTEVAL S3 SCNSN SCANSHIFTEN Q5 SD 0 SDATA 0 AA35 SD 1 SDATA 1 W37 SD 2 SDATA 2 W35 Table 23 Pin Name Abbreviations continued Abbreviation Full Name Pin SD 3 SDATA 3 Y35 SD 4 S...

Страница 71: ...INCLK 0 W33 SDIC 1 SDATAINCLK 1 J35 SDIC 2 SDATAINCLK 2 E27 SDIC 3 SDATAINCLK 3 E15 SDINV SDATAINVALID AN33 SDOC 0 SDATAOUTCLK 0 AE35 SDOC 1 SDATAOUTCLK 1 C37 Table 23 Pin Name Abbreviations continued...

Страница 72: ...CORE T36 VCC VCC_CORE V2 VCC VCC_CORE V4 VCC VCC_CORE V6 VCC VCC_CORE V8 Table 23 Pin Name Abbreviations continued Abbreviation Full Name Pin VCC VCC_CORE X30 VCC VCC_CORE X32 VCC VCC_CORE X34 VCC VCC...

Страница 73: ...AJ23 VID 0 L1 VID 1 L3 VID 2 L5 VID 3 L7 VID 4 J7 VREF_S VREF_SYS W5 VSS B2 VSS B6 VSS B10 VSS B14 VSS B18 VSS B22 VSS B26 VSS B30 VSS B34 VSS D6 VSS D10 VSS D14 VSS D18 Table 23 Pin Name Abbreviation...

Страница 74: ...VSS AB4 VSS AB6 VSS AD32 VSS AD34 VSS AD36 VSS AF2 VSS AF4 VSS AF12 VSS AF16 VSS AH12 VSS AH16 VSS AH20 VSS AH24 VSS AH28 VSS AH32 VSS AH34 Table 23 Pin Name Abbreviations continued Abbreviation Full...

Страница 75: ...push pull mode driven by a single source O indicates open drain mode that allows devices to share the pin Note The AMD Athlon processor supports push pull drivers For more information see Push Pull PP...

Страница 76: ...P A35 SDATA 40 P B G A37 SDATA 30 P B P B2 VSS B4 VCC_CORE B6 VSS B8 VCC_CORE B10 VSS B12 VCC_CORE B14 VSS B16 VCC_CORE B18 VSS B20 VCC_CORE B22 VSS B24 VCC_CORE B26 VSS B28 VCC_CORE B30 VSS B32 VCC_...

Страница 77: ...SDATA 46 P B P E25 NC Pin page 76 E27 SDATAINCLK 2 P I G E29 SDATA 33 P B P E31 SDATA 32 P B P Table 24 Cross Reference by Pin Location Pin Name Description L P R E33 NC Pin page 76 E35 SDATA 31 P B P...

Страница 78: ...in page 76 H32 NC Pin page 76 H34 VSS H36 VSS J1 SADDOUT 0 page 77 P O J3 SADDOUT 1 page 77 P O Table 24 Cross Reference by Pin Location Pin Name Description L P R J5 NC Pin page 76 J7 VID 4 page 77 O...

Страница 79: ...G Q37 SDATA 16 P B G R2 VCC_CORE R4 VCC_CORE R6 VCC_CORE R8 VCC_CORE R30 VSS R32 VSS Table 24 Cross Reference by Pin Location Pin Name Description L P R R34 VSS R36 VSS S1 SCANCLK1 page 77 P I S3 SCA...

Страница 80: ...age 76 Y33 NC Pin page 76 Y35 SDATA 3 P B G Y37 SDATA 12 P B P Z2 VCC_CORE Z4 VCC_CORE Table 24 Cross Reference by Pin Location Pin Name Description L P R Z6 VCC_CORE Z8 VCC_CORE Z30 VSS Z32 VSS Z34 V...

Страница 81: ...AF28 NC Pin page 76 Table 24 Cross Reference by Pin Location Pin Name Description L P R AF30 NC Pin page 76 AF32 NC Pin page 76 AF34 VCC_CORE AF36 VCC_CORE AG1 FERR page 73 P O AG3 RESET I AG5 NC Pin...

Страница 82: ...DIN 0 page 77 P I AJ31 SFILLVALID P I G AJ33 SADDINCLK P I G AJ35 SADDIN 6 P I P AJ37 SADDIN 3 P I G Table 24 Cross Reference by Pin Location Pin Name Description L P R AK2 VSS AK4 VSS AK6 CPU_PRESENC...

Страница 83: ...6 VCC_CORE AM28 VSS AM30 VCC_CORE AM32 VSS AM34 VCC_CORE AM36 VSS AN1 No Pin page 76 AN3 NMI P I AN5 SMI P I AN7 NC Pin page 76 AN9 NC Pin page 76 Table 24 Cross Reference by Pin Location Pin Name Des...

Страница 84: ...Duron System Bus Specification order 21902 for information about the system bus pins PROCRDY PWROK RESET SADDIN 14 2 SADDINCLK SADDOUT 14 2 SADDOUTCLK SDATA 63 0 SDATAINCLK 3 0 SDATAINVALID SDATAOUTCL...

Страница 85: ...vide processor core voltage feedback to the system CPU_PRESENCE Pin CPU_PRESENCE is connected to VSS on the processor package If pulled up on the motherboard CPU_PRESENCE may be used to detect the pre...

Страница 86: ...about Serialization Initialization Packets and SIP protocol The processor FID 3 0 outputs are open drain and 2 5 V tolerant To prevent damage to the processor do not pull these Table 25 FID 3 0 Clock...

Страница 87: ...ont side bus FSB setting of this processor Proper detection of the FSB setting requires the implementation of a pull up resistor on the motherboard Refer to the AMD Athlon Processor Based Motherboard...

Страница 88: ...GA key pins only where designated However sockets that populate all 16 key pins must be allowed so the motherboard must always provide for pins at all key pin locations See NC Pins for more informatio...

Страница 89: ...YSCLK and SYSCLK SYSCLK and SYSCLK are differential input clock signals provided to the PLL of the processor from a system clock generator See CLKIN RSTCLK SYSCLK Pins on page 73 for more information...

Страница 90: ...24363 ZN and ZP Pins ZN AC5 and ZP AE5 are the push pull compensation circuit pins In Push Pull mode selected by the SIP parameter SysPushPull asserted ZN is tied to VCC_CORE with a resistor that has...

Страница 91: ...4 OPN1 Advanced Front Side Bus D 333 E 400 Size of L2 Cache 4 512 Kbytes Die Temperature V 85 C Operating Voltage K 1 65 V Package Type D OPGA Model Number 2500 operates at 1833 MHz2 2600 at 1917 MHz2...

Страница 92: ...80 Ordering Information Chapter 12 AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 93: ...10 For electrical information about this thermal diode see Table 13 Thermal Diode Electrical Characteristics on page 37 Ideal Diode Equation The ideal diode equation uses the variables and constants d...

Страница 94: ...Correction A temperature offset may be required to correct the value measured by a temperature sensor An offset is necessary if a difference exists between the lumped ideality factor of the processor...

Страница 95: ...r further details Equation 3 shows the equation for calculating the lumped ideality factor nf lumped in sensors that do not employ series resistance cancellation Equation 4 shows the equation for calc...

Страница 96: ...84 Appendix A Thermal Diode Calculations AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

Страница 97: ...lowest signal numbers are contained in brackets and separated by a colon for example D 63 0 Reserved Bits and Signals Signals or bus bits marked reserved must be driven inactive or left unconnected as...

Страница 98: ...gnificant byte position little end In byte diagrams bit positions are numbered from right to left the little end is on the right and the big end is on the left Data structure diagrams in memory show l...

Страница 99: ...in this document Table 30 Abbreviations Abbreviation Meaning A Ampere F Farad G Giga Gbit Gigabit Gbyte Gigabyte GHz Gigahertz H Henry h Hexadecimal K Kilo Kbyte Kilobyte lbf Foot pound M Mega Mbit Me...

Страница 100: ...terconnect API Application Programming Interface APIC Advanced Programmable Interrupt Controller BIOS Basic Input Output System BIST Built In Self Test BIU Bus Interface Unit CPGA Ceramic Pin Grid Arr...

Страница 101: ...Open Drain OPGA Organic Pin Grid Array PA Physical Address PBGA Plastic Ball Grid Array PCI Peripheral Component Interconnect PDE Page Directory Entry PDT Page Directory Table PGA Pin Grid Array PLL P...

Страница 102: ...n SRAM Synchronous Random Access Memory SROM Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory TTL Transistor Transistor Logic VAS Virtual Address Space VPA Virtual Page Addre...

Страница 103: ...Web site http www amd com AMD Athlon Processor x86 Code Optimization Guide order 22007 AMD Processor Recognition Application Note order 20734 Methodologies for Measuring Temperature on AMD Athlon and...

Страница 104: ...92 Appendix B Conventions and Abbreviations AMD Athlon XP Processor Model 10 Data Sheet 26237C May 2003 Preliminary Information...

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