101 Innovation Drive
San Jose, CA 95134
www.altera.com
SDI HSMC Reference Manual
Document Version:
1.0
Document Date:
July 2009
Страница 1: ...101 Innovation Drive San Jose CA 95134 www altera com SDI HSMC Reference Manual Document Version 1 0 Document Date July 2009...
Страница 2: ...gn patents and pending ap plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty bu...
Страница 3: ...Status Elements 2 5 Clock Circuitry 2 6 SDI Clock 2 6 Host Board Reference Clock 2 10 Loop Back Reference Clock From SDI Input 2 11 Studio Reference Timing 2 11 Studio Reference Video Timing 2 11 AES3...
Страница 4: ...iv SDI HSMC Reference Manual July 2009 Altera Corporation...
Страница 5: ...High frequency switching regulator LT3480 for 12 V to 5 V power conversion Three linear regulators LT3080 for 5 V to 3 3 V low noise power conversion FDTIM analysis for power distribution network PDN...
Страница 6: ...e Stratix IV GX FPGA Development Board Reference Manual Development Board Block Diagram Figure 1 2 shows the functional block diagram of the SDI HSMC The board has three distinct areas of interest SDI...
Страница 7: ...output of the chipset is fed into a differential clock buffer The differential signal is then output to the HSMC connector and SMA connectors Two crystal oscillators are used in this chipset 27 MHz an...
Страница 8: ...between 40 C and 100 C The recommended operating temperature is between 0 C and 55 C Figure 1 2 SDI HSMC Block Diagram TX 1 DATA SDI TX 1 EQ 1 SDI RX 1 Video Sync Separator Video In 148 5 MHz HSYNC VS...
Страница 9: ...and installing the demonstration software refer to the Audio Video Development Kit Stratix IV GX Edition User Guide This chapter consists of the following sections Board Overview Supported Protocols o...
Страница 10: ...SDI Cable Tri speed Driver U1 AES Output Channel 1 J3 AES Input Channel 1 J10 AES Output Channel 2 J14 AES Input Channel 2 J15 SDI Output Channel 2 J1 Carrier Detect Mute Jumper J4 SDI Input Channel...
Страница 11: ...ifferential line driver and receiver for the AES interface U11 U12 U13 Linear regulator Regulator with an input of 5 V and output of 3 3 V U14 U15 Single gate tri state buffer For AES VCXO control SDI...
Страница 12: ...ected from J9 for channel 1 Removing a jumper from J6 causes the mute function to be enabled Altera recommends to leave this jumper installed J4 SDI input 2 auto mute enable jumper Installing a jumper...
Страница 13: ...mper configuration has J4 CD_MUTE2 and J6 CD_MUTE1 installed Jumpers J5 EQ_BYPASS2 and J7 EQ_BYPASS1 can be driven from the host board These signals bypass the SDI cable equalizer when logic 1 is driv...
Страница 14: ...nel 1 D7 Green LED Illuminates when 3 3 V SDI power is active D8 Green LED Illuminates when 3 3 V AES power is active D9 Green LED Illuminates when 5 V power is active D12 Green LED Illuminates when 3...
Страница 15: ...by the internal VCXO Clock inputs to the SDI PLL come from the HSMC host or through an SMA input Both inputs are end terminated at 50 to ground The HSMC signal SDI_CLK_SEL determines which input is a...
Страница 16: ...CXO is locked to 27 MHz or alternate the signal is then multiplied up to the output frequency by the femto clock PLL refer to Table 2 6 The output frequency can be 148 5 MHz 74 25 MHz 54 MHz or 36 MHz...
Страница 17: ...7 MHz 0101 4004 4004 27 MHz 27 MHz 26 973 MHz 26 973 MHz 0110 4004 4000 27 MHz 26 973 MHz 0111 1000 1001 26 973 MHz 27 MHz 1000 250 91 74 175 MHz 27 MHz 1001 253 92 74 25 MHz 27 MHz 1010 92 92 27 MHz...
Страница 18: ...nectors These outputs serve as a low jitter source to sync up other system devices and to trigger on test equipment or alternate reference clock source to the host board Host Board Reference Clock You...
Страница 19: ...ampling from a 16 384 MHz crystal Most combinations are available at outputs CLK1 and CLK2 Output CLK1 is connected to the HSMC connector and drives a signal to the host device Output CLK2 is connecte...
Страница 20: ...3 PLL1 PLL2 PLL3 One time programmable ROM with PLL Values Divide Logic and Output Enable Control CLK1 CLK2 CLK3 CLK4 PDTS GND External Capacitors S2 S0 VDD X1 X2 VIN 3 Table 2 9 Audio Sample Rate ve...
Страница 21: ...of the most popular audio sample rates 176 4 22 5792 5 112 8960 192 24 5760 5 122 8800 Table 2 10 VCXO PLL Frequency Output S2 S1 S0 CLK1 MHz CLK2 MHz CLK3 CLK4 0 0 0 98 304 98 304 OFF OFF 0 0 1 90 31...
Страница 22: ...re normally not installed If the HSMC host does not drive this signal then the SDI cable equalizer is in bypass mode The RX channel receives 270 Mbps 1 485 Gbps and 2 970 Gbps SDI signals through a si...
Страница 23: ...ntitled SDI Cable Driver on page 5 of Altera schematic 150 0320610 B1 In Altera development kits that contain the SDI HSMC this schematic resides in the install dir board_design_files directory The SD...
Страница 24: ...s should not be installed with DC blocking capacitors If DC blocking capacitors are installed remove the capacitors and install 0 resistors of the same foot print size 0402 The input of the SDI cable...
Страница 25: ...ed LVCMOS signal which is driven to the host board through the HSMC connector Figure 2 9 shows the AES3 RX channel block diagram AES3 TX Channels The AES3 TX channel is designed to have a balanced sig...
Страница 26: ...channels 1 and 2 In the factory default board configuration jumpers are installed on the CD_MUTE jumper switches J4 and J6 and not installed on the EQ_BYPASS jumper switches J5 and J7 When jumpers ar...
Страница 27: ...jumper is normally installed Signal short J5 EQ_BYPASS2 Equalizer bypass for RX channel 2 The equalizer can be bypassed manually when EQ_BYPASS2 signal is tri stated This jumper is normally not insta...
Страница 28: ...or Bank 1 Pin Outs NC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 NC NC NC NC NC NC NC NC NC NC NC JTAG_TDO_TDI NC NC NC NC NC NC NC...
Страница 29: ...2 V 12 V 12 V 12 V 12 V AES_CLK 12 V 12 V 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 SDI_LED_TX_R1 SDI_LED_TX_R2 3 3 V SDI_LED_TX_G1 SDI_LED_TX_G2 SDI_LE...
Страница 30: ...28 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 AES_OUT1 AES_OUT2 AES_VCXO_UP AES_VCXO_DN SDI_CLK_SEL SDI_XTAL_SEL SDI_CLK_BP0 SDI_CLK_BP1 SDI_CLK_N0 SDI_CLK_N1 SDI_CLK_V0 SDI_CLK_V...
Страница 31: ..._TX_G1 Green LED signal for transmit channel 1 Input 47 CMOS SDI_LED_TX_G2 Green LED signal for transmit channel 2 Input 49 CMOS SDI_LED_RX_R1 Red LED signal for receive channel 1 Input 59 CMOS SDI_LE...
Страница 32: ...t 151 CMOS SDI_HSMC_CLK SDI chip reference clock input Input 155 CMOS AES_CLK AES clock reference Output 96 CMOS AES_IN1 AES data input 1 Output 102 CMOS AES_IN2 AES data input 2 Output 104 CMOS ODDEV...
Страница 33: ...settings perform the following steps Install jumpers J4 and J6 CD_MUTE Remove all other jumpers Figure 2 14 Power Distribution System 12 V Input from HSMC 12 W 1 A 12 V High Frequency Switching Regul...
Страница 34: ...2 26 Chapter 2 Board Components Restoring Board to Factory Defaults SDI HSMC Reference Manual July 2009 Altera Corporation...
Страница 35: ...ocument Version Changes Made Summary of Changes July 2009 v1 0 Initial release Contact Note 1 Contact Method Address Technical support Website www altera com support Technical training Website www alt...
Страница 36: ...ections within a document and titles of Quartus II Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and i...
