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DE1-SoC Computer System
with Nios II

For Quartus II 15.0

1

Introduction

This document describes a computer system that can be implemented on the Altera DE1-SoC development and
education board. This system, called the

DE1-SoC Computer

, is intended for use in experiments on computer orga-

nization and embedded systems. To support such experiments, the system contains embedded processors, memory,
audio and video devices, and some simple I/O peripherals. The FPGA programming file that implements this system,
as well as its design source files, can be obtained from the University Program section of Altera’s web site.

2

DE1-SoC Computer Contents

A block diagram of the DE1-SoC Computer system is shown in Figure

1

. As indicated in the figure, the components

in this system are implemented utilizing both the FPGA and the

Hard Processor System

(HPS) inside Altera’s

Cyclone

R

°

V SoC chip. The FPGA implements two Nios II processors and several peripheral ports: memory, timer

modules, audio-in/out, video-in/out, PS/2, analog-to-digital, infrared receive/transmit, and parallel ports connected
to switches and lights. The HPS comprises an ARM Cortex A9 dual-core processor and a set of peripheral devices.
Instructions for using the HPS and ARM processor are provided in a separate document, called

DE1-SoC Computer

System with ARM Cortex-A9

.

2.1

FPGA Components

As shown in Figure

1

many of the components in the DE1-SoC Computer are implemented inside the FPGA in the

Cyclone V SoC chip. Several of these components are described in this section, and the others are presented in
Section

4

.

2.2

Nios II Processor

The Altera Nios

R

°

II processor is a 32-bit CPU that can be implemented in an Altera FPGA device. Three versions

of the Nios II processor are available, designated economy (/e), standard (/s), and fast (/f). The DE1-SoC Computer
includes two Nios II processors, both of which are the fast version.

An overview of the Nios II processor can be found in the document

Introduction to the Altera Nios II Processor

,

which is provided in the University Program’s web site. An easy way to begin working with the DE1-SoC Computer
and the Nios II processor is to make use of a utility called the

Altera Monitor Program

. It provides an easy way to

assemble/compile Nios II programs written in either assembly language or the C language. The Monitor Program,
which can be downloaded from Altera’s web site, is an application program that runs on the host computer connected
to the DE1-SoC board. The Monitor Program can be used to control the execution of code on Nios II, list (and

Altera Corporation - University Program

2015

1

Содержание DE1-SoC

Страница 1: ...tions for using the HPS and ARM processor are provided in a separate document called DE1 SoC Computer System with ARM Cortex A9 2 1 FPGA Components As shown in Figure 1 many of the components in the D...

Страница 2: ...includes the DE1 SoC Computer as a predesigned system that can be downloaded onto the DE1 SoC board as well as several sample programs in assembly language and C that show how to use the DE1 SoC Comp...

Страница 3: ...mplemented inside the FPGA that is used as a character buffer for the video out port which is described in Section 4 2 The character buffer memory is organized as 8K x 8 bits and spans the address ran...

Страница 4: ...o parallel ports connected to the 7 segment displays on the DE1 SoC board each of which comprises a 32 bit write only Data register As indicated in Figure 4 the register at address 0xFF200020 drives d...

Страница 5: ...nused KEY3 0 Edge bits Mask bits Unused Unused Unused Data register Interruptmask register Edgecapture register Unused Figure 6 Registers used in the pushbutton parallel port 2 4 5 Expansion Parallel...

Страница 6: ...rograms perform the same operations and illustrate the use of parallel ports by using either assembly language or C code The code in the figures displays the values of the SW switches on the red light...

Страница 7: ...movia r20 0xFF200020 HEX3_HEX0 base address movia r19 HEX_bits ldwio r6 0 r19 load pattern for HEX displays DO_DISPLAY ldwio r4 0 r15 load input from slider switches stwio r4 0 r16 write to red LEDs l...

Страница 8: ...FF200040 SW slider switch address volatile int KEY_ptr int 0xFF200050 pushbutton KEY address int HEX_bits 0x0000000F initial pattern for HEX displays int SW_value volatile int delay_count volatile so...

Страница 9: ...h is provided in bits 7 0 decrements the value of RAVAIL by one and returns this decremented value as part of the read operation If no data is present in the receive FIFO then RVALID will be set to 0...

Страница 10: ...cter data back to the JTAG UART text executable code follows global _start _start set up stack pointer movia sp 0x03FFFFFC put stack at top of SDRAM movia r6 0xFF201000 JTAG UART base address print a...

Страница 11: ...stw r4 0 sp save register ldwio r4 4 r6 read the JTAG UART Control register andhi r4 r4 0xffff check for write space beq r4 r0 END_PUT if no space ignore the character stwio r5 0 r6 send the character...

Страница 12: ...TAG UART example code n 0 char str c print a text string for str text_string str 0 str put_jtag str read and echo characters while 1 c get_jtag if c 0 put_jtag c Subroutine to send a character to the...

Страница 13: ...ly counting ITO is used for generating interrupts which are discussed in section 3 CONT affects the continuous operation of the timer When the timer reaches a count value of zero it auto matically rel...

Страница 14: ...SoC Computer is set to 0x00000000 The address used for all other general exceptions such as divide by zero and hardware IRQ interrupts is 0x00000020 Since the Nios II processor uses the same address...

Страница 15: ...hbutton parallel port The Interruptmask register allows inter rupts to be generated when a key is pressed Each bit in the Edgecapture register is set to 1 by the parallel port when the corresponding k...

Страница 16: ...in the interval timer that causes an interrupt to occur every 33 msec equ KEY2 1 This program demonstrates use of interrupts in the DE1 SoC Computer It first starts the interval timer with 33 msec tim...

Страница 17: ...show on the HEX displays global KEY_PRESSED KEY_PRESSED word KEY2 stores code representing pushbutton key pressed global SHIFT_DIR SHIFT_DIR word 2 default shift direction 2 right end Figure 16 An exa...

Страница 18: ...xecutable section exceptions ax global EXCEPTION_HANDLER EXCEPTION_HANDLER subi sp sp 16 make room on the stack stw et 0 sp rdctl et ctl4 beq et r0 SKIP_EA_DEC interrupt is not external subi ea ea 4 m...

Страница 19: ...ldw r22 12 sp addi sp sp 16 eret end Figure 17 Reset and exception handler assembly language code Part b include key_codes s includes equ for KEY0 KEY1 extern PATTERN externally defined variables exte...

Страница 20: ...6 0 r21 load pattern for HEX displays stwio r6 0 r20 store to HEX3 HEX0 ldw r4 0 r22 check which key has been pressed CHK_KEY0 movi r8 KEY0 code to check for KEY1 bne r4 r8 CHK_KEY1 movia r20 SLIDER_S...

Страница 21: ...e the displayed pattern right br END_INTERVAL_TIMER_ISR SHIFT_L movi r8 LEFT bne r5 r8 END_INTERVAL_TIMER_ISR movi r5 1 set r5 to the constant value 1 rol r6 r6 r5 shift left END_INTERVAL_TIMER_ISR st...

Страница 22: ...of pushbutton KEY parallel port ldwio r11 0xC r10 read edge capture register stwio r0 0xC r10 clear the interrupt movia r10 KEY_PRESSED global variable to return the result CHECK_KEY0 andi r13 r11 0b0...

Страница 23: ...tion called the_reset provides a simple reset mechanism by performing a branch to the main program The function named the_exception represents a general exception handler that can be used with any C p...

Страница 24: ...e displayed pattern to the right KEY 2 rotates the displayed pattern to the left KEY 3 stops the rotation int main void Declare volatile pointers to I O registers volatile means that IO load and store...

Страница 25: ...NIOS2_READ_ESTATUS dest do dest __builtin_rdctl 1 while 0 define NIOS2_READ_BSTATUS dest do dest __builtin_rdctl 2 while 0 define NIOS2_READ_IENABLE dest do dest __builtin_rdctl 3 while 0 define NIOS2...

Страница 26: ...handles Nios II exception processing This code should not be modified instead the C language code in the function interrupt_handler can be modified as needed for a given application void the_exceptio...

Страница 27: ...asm stw r21 84 sp asm stw r22 88 sp asm stw r23 92 sp asm stw r25 100 sp r25 bt skip r24 et because it was saved above asm stw r26 104 sp r26 gp skip r27 because it is sp and there is no point in savi...

Страница 28: ...7 because it is sp and we did not save this on the stack asm ldw r28 112 sp r28 fp asm ldw r29 116 sp r29 ea asm ldw r30 120 sp r30 ba asm ldw r31 124 sp r31 ra asm addi sp sp 128 asm eret Interrupt S...

Страница 29: ...0020 HEX3_HEX0 address interval_timer_ptr 0 clear the interrupt HEX3_HEX0_ptr pattern display pattern on HEX3 HEX0 rotate the pattern shown on the HEX displays if key_pressed KEY0 for KEY0 load a new...

Страница 30: ...variable KEY_PRESSED void pushbutton_ISR void volatile int KEY_ptr int 0xFF200050 int press press KEY_ptr 3 read the pushbutton interrupt register KEY_ptr 3 press clear the interrupt if press 0x1 KEY0...

Страница 31: ...by removing data from the Read FIFOs until both are less than 75 full Bit WE gives an interrupt enable capability for outgoing data Setting this bit to 1 allows the audio core to generate an interrupt...

Страница 32: ...a VGA controller that can be connected to a standard VGA monitor The VGA controller supports a screen resolution of 640 480 The image that is displayed by the VGA controller is derived from two sourc...

Страница 33: ...ory for display on the VGA screen You can modify the pixel data at any time simply by writing to the pixel addresses Thus an image can be changed even when it is in the process of being displayed Howe...

Страница 34: ...ddress 0 15 31 0xFF203020 0xFF203024 A S 1 X Y 16 2 23 front buffer address 0xFF203028 back buffer address 0xFF20302C 3 B 7 m n 4 8 24 Backbuffer register Resolution register Status register Buffer re...

Страница 35: ...of Figure 30 shows that characters are addressed in the memory by using the combination of a base address which has the value 09000000 16 and an x y offset Using this scheme the character at location...

Страница 36: ...be displayed on a VGA monitor by using the video out port described in Section 4 2 The video in port writes each frame of the video in data into the pixel buffer described in Section 4 2 1 The video...

Страница 37: ...e 33 The PS2_Data register is both readable and writable When bit 15 RVALID is 1 reading from this register provides the data at the head of the FIFO in the Data field and the number of entries in the...

Страница 38: ...port shown in Figure 34 except that the base address of its PS2_Data register is 0xFF200108 and the base address of its PS2_Control register is 0xFF20010C 4 6 IrDA Infrared Serial Port The IrDA port...

Страница 39: ...ding interrupts are indicated in the Control register s RI and WI bits and can be cleared by writing or reading data to from the UART 4 7 Analog to Digital Conversion Port The Analog to Digital Conver...

Страница 40: ...s Quartus II software and Qsys tool Tutorials that introduce this software are provided in the University Program section of Altera s web site To modify the system it is first necessary to make an edi...

Страница 41: ...results on Terminal window int main void float x y add sub mult div while 1 printf Enter FP values X Y n scanf f x printf f x echo the typed data to the Terminal window scanf f y printf f n y echo the...

Страница 42: ...004F Slider Switches 0xFF200050 0xFF20005F Pushbutton KEYs 0xFF200060 0xFF20006F JP1 Expansion 0xFF200070 0xFF20007F JP2 Expansion 0xFF200100 0xFF200107 PS 2 0xFF200108 0xFF20010F PS 2 Dual 0xFF201000...

Страница 43: ...ing used Pressing Next opens the window in Figure 40 Here the user can select the DE1 SoC Computer as a predesigned system The Monitor Program then fills in the relevant information in the System deta...

Страница 44: ...ns of the Monitor Program Figure 42 gives the final screen that is used to create a new project in the Monitor Program This screen shows the default addresses of compiler and linker sections that will...

Страница 45: ...DE1 SOC COMPUTER SYSTEM WITH NIOS II For Quartus II 15 0 Figure 41 Selecting sample programs Figure 42 Setting offsets for text and data Altera Corporation University Program 2015 45...

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