Write Data Buffer
The write data buffer receives write data from the MPFE and passes the data to the PHY, on approval of the
write request.
ECC Block
The ECC block consists of an encoder and a decoder-corrector, which can detect and correct single-bit
errors, and detect double-bit errors. The ECC block can correct single- bit errors and detect double-bit errors
resulting from noise or other impairments during data transmission.
AFI Interface
The AFI interface provides communication between the controller and the PHY.
CSR Interface
The CSR interface is accessible from the L4 bus. The interface allows code executing in the HPS MPU and
FPGA fabric to configure and monitor the SDRAM controller.
Functional Description of the SDRAM Controller Subsystem
MPFE Operation Ordering
Requests to the same SDRAM page arriving at a given port are executed in the order in which they are
received. Requests arriving at different ports have no guaranteed order of service, except when a first
transaction has completed before the second arrives.
Operation ordering is defined and enforced within a port, but not between ports. All transactions received
on a single port for overlapping addresses execute in order. Transactions received on different ports have
no guaranteed order unless the second transaction is presented after the first has completed.
Avalon-MM does not support write acknowledgement. When a port is configured to support Avalon-MM,
you should read from the location that was previously written to ensure that the write operation has completed.
When a port is configured to support AXI, the master accessing the port can safely issue a read operation
to the same address as a write operation as soon as the write has been acknowledged. To keep write latency
low, writes are acknowledged as soon as the transaction order is guaranteed—meaning that any operations
received on any port to the same address as the write operation are executed after the write operation.
To ensure that the overall latency of traffic is as low as possible, the single port logic can return read data
out of order to the multi-port logic which will reorder it when transactions return out of order. A large
percentage of traffic reordering will be between ports and transactions only are ordered within a port. For
traffic which is reordered between ports but not within a port, no reordering needs to be done. Eliminating
unnecessary reordering reduces average latency.
MPFE Multiport Scheduling
Multiport scheduling is governed by two factors, the absolute priority of a request and the weighting of a
port.
The evaluation of absolute priority ensures that ports carrying higher-priority traffic are served ahead of
ports carrying lower-priority traffic. The scheduler recognizes eight priority levels (0-7), with higher values
representing higher priorities. For example, any transaction with priority seven is scheduled before
transactions of priority six or lower.
Altera Corporation
SDRAM Controller Subsystem
8-7
Functional Description of the SDRAM Controller Subsystem
cv_54008
2013.12.30
