Altair ALT1210MOD-VZ-01, Руководство пользователя, Страница: 11 / 18

ALT1210MOD-VZ-01 User Module Rev 1.0
Altair Semiconductor Proprietary and Confidential 11
3.3. Pins Description
Pin name Pin Description Pin count
VBAT Main module supply 3.4-4.2V
VPA RF PA output stage supply 3.4-4.2V
1v8_IO_IN 1.8V input for module interface IOs
VDD_RET_IN 1.8V input for DDR supply (can be supplied from !V8_IO or from VO18R)
WAKEUP Signal from host to wakeup modem (active high)
HOST_WAKEUP Signal from modem to wakeup host (active high)
SHUTDOWN Signal from host to shutdown modem (active high)
RETLE_N_IN DDR retention control (Input)
RETLE_N_OUT Default DDR retention control signal (Output)
RSTN Digital reset signal
ALARMZ Optional control line for external module power supply (high=OFF, Low=ON), open drain
UIM_VCC power supply output for external SIM card
UIM_CLK SIM interface clock signal
UIM_DATA SIM interface data signal
UIM_RESET SIM interface reset signal
UIM_DETECT SIM interface detect signal (Active high)
USB20_DP USB interface possitive signal (differential)
USB20_DN USB interface negative signal (differential)
UART2_TX UART2 TX pin (output)
UART2_RX UART2 TX pin (input)
UART1_TX UART1 TX pin (output)
UART1_RX UART1 RX pin (input)
UART1_RTS UART1 RTS pin (output)
UART1_CTS UART1 RTS pin (input)
I2C_SDA I2C interface data signal
I2C_SCL I2C interafce clock signal
FLASH_1V8_OUT Internal 1.8V digital supply rail
SF_CLK Serial flash clock signal
SF_SI/IO0 Serial flash data in signal
SF_SO/IO1 Serial flash data out signal
SF_nWP/IO2 Serial flash write protect signal
SF_nHOLD/IO3 Serial flash HOLD signal
SF_nCS1 Serial flash chips select signal
SPI_M_CLK SPI master interface clock signal
SPI_M_MOSI SPI master interface data out signal
SPI_M_MISO SPI master interface data in signal
SPI_M_EN_1 SPI master interface enable pin signal
SAR_VAINP0 ADC input
SAR_VAINP1 ADC input
SAR_VAINP2 ADC input
SAR_VAINP3 ADC input
PCM_CLK GPIO or PCM interface clock signal
PCM_OUT GPIO or PCM interface data out signal
PCM_IN GPIO or PCM interface data in signal
PCM_FS GPIO or PCM interface frame sync signal
SPI_S_MISO GPIO or SPI slave data out signal
SPI_S_MOSI GPIO or SPI slave data in signal
SPI_S_CS GPIO or SPI slave chip select signal
SPI_S_RDY GPIO or SPI slave ready signal
SPI_S_CLK GPIO or SPI slave clk signal
SPI_M_EN_2 GPIO or SPI master enable2 signal
GPIO11 GPIO
GPIO12 GPIO
UART1_DTR GPIO or Fast UART DTR signal (input)
UART1_RING GPIO or Fast UART RING signal (output)
UART1_DCD GPIO or Fast UART DCD signal (output)
UART1_DSR GPIO or Fast UART DSR signal (output)
FEM_CTRL0 FEM control, GPIO or optional source for the RETLE_N_INPUT
FEM_CTRL1 FEM control or GPIO
FEM_CTRL2 FEM control or GPIO
FEM_CTRL3 FEM control or GPIO
FEM_CTRL4 FEM control or GPIO
FEM_CTRL5 FEM control or GPIO
FEM_CTRL6 FEM control or GPIO
FEM_CTRL7 FEM control or GPIO
Reserved pins NC These pins should be kept unconnected 11
RF ANT RF antenna for RX/TX 1
Ground Ground 57
Total Functional 137
7 Control pins
SAR ADC 4
Digital IOs (GPIOs and Interfaces) 16
SPI Master 4
UART2
UART1 4
2
2
8 FEM controls
Serial Flash 7
SIM 5
7
USB 2
I2C
Power Supply Inputs