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ADM-XRC-9R1 User Manual
V1.7 - 16th Sept 2020

3.4.3 PN6 Reference Clock (PN6_PCIEREFCLK)

The reference clock "PN6_PCIEREFCLK" is a differential clock provided by a carrier card through the Secondary

XMC connector P6 at pins A19 and B19. This board connects this pair to an MGT clock input.

Signal

Frequency

FPGA Input

IO Standard

"P" pin

"N" pin

PN6_PCIEREFCLK

100 MHz

MGTREFCLK1_129

LVDS

F28

F29

Table 7 : PN6_PCIEREFCLK Connections

3.4.4 Programmable Clocks (PROGCLK 0-2)

There is one programmable clock source that is forwarded throughout the FPGA. This clock is programmable

through the USB system monitor. PROGCLK[2:0] is generated by a dedicated programmable clock generator IC

and offer extremely high frequency resolutions (1ppm increments). PROGCLK[2:0] are all buffered copies of the

same clock signal.

Signal

Frequency

Target FPGA Input

IO Standard

"P" pin

"N" pin

PROGCLK0

5 - 312.5 MHz

PS_MGTREFCLK1_505 LVDS

V29

V30

PROGCLK1

5 - 312.5 MHz

MGTREFCLK0_128

LVDS

M28

M29

PROGCLK2

5 - 312.5 MHz

IO_L8P_HDGC_89

LVDS

G11

G10

Table 8 : PROGCLK Connections

3.4.5 MGT Reference Clocks

The PS and PL MGTs can be clocked by sources from the P5, P6 or on-board clock sources

Zynq Ultrascale

MGT Banks

MGT129

REFCLK0

REFCLK1

MGT128

XMC

PCIe

REFCLK

Buffer

Programmable

Clock Source

REFCLK0
REFCLK1

MGT505

REFCLK2

REFCLK0

REFCLK1

Figure 5 : MGT Clocks

Page 11

Functional Description
ad-ug-1353_v1_7.pdf

Содержание ADM-XRC-9R1

Страница 1: ...ADM XRC 9R1 User Manual Document Revision 1 7 16th Sept 2020...

Страница 2: ...r form without prior written consent from Alpha Data Parallel Systems Ltd Head Office Address Suite L4A 160 Dundee Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sale...

Страница 3: ...3 3 JTAG Voltages 9 3 4 Clocks 10 3 4 1 300MHz Reference Clocks REFCLK300M and FABRIC_CLK 10 3 4 2 PCIe Reference Clocks PCIEREFCLK 10 3 4 3 PN6 Reference Clock PN6_PCIEREFCLK 11 3 4 4 Programmable C...

Страница 4: ...11 Table 9 Reference clocks Connections 12 Table 10 RF Clock Connections 12 Table 11 SysRef Connections 13 Table 12 FPGA Reference Clock Connections 13 Table 13 FPGA 4 Wire Connections 14 Table 14 Bo...

Страница 5: ...Interfaces 16 Figure 9 Serial COM Ports 16 Figure 10 USB Interfaces 17 Figure 11 MGT Links 18 Figure 12 PL DRAM Banks 19 Figure 13 GPIO Block Diagram 19 Figure 14 Front Panel IO 20 Figure 15 ADM XRC 9...

Страница 6: ...ADM XRC 9R1 User Manual V1 7 16th Sept 2020 Page Intentionally left blank...

Страница 7: ...l COM port interfaces to rear P4 connector One system monitor USB port to micro USB connector Two Gigabit Ethernet interfaces to rear P4 connector 4 lane PCI Express Gen 2 interface on the P5 connecto...

Страница 8: ...tocol Layer Standard Feb 2006 VITA ISBN 1 885731 41 8 ANSI VITA 42 3 XMC PCI Express Protocol Layer Standard June 2006 VITA ISBN 1 885731 43 4 ANSI VITA 46 9 PMC XMC Rear I O Fabric Signal Mapping on...

Страница 9: ...d P4 connectors The motherboard carrier must comply with the XMC 3 VITA 42 3 specification for the Primary XMC connector J5 The Secondary XMC connector P6 has a pinout compatible with various XMC to V...

Страница 10: ...to the order number given at time of purchase It is the users responsibility to ensure sufficient airflow for air cooled applications and metalwork for conduction cooled applications For more details...

Страница 11: ...ADM XRC 9R1 User Manual V1 7 16th Sept 2020 3 Functional Description 3 1 Overview Figure 1 ADM XRC 9R1 Block Diagram Page 5 Functional Description ad ug 1353_v1_7 pdf...

Страница 12: ...N State Off State SW1 1 BootMode 0 See Table 14 SW1 2 BootMode 1 See Table 14 SW1 3 BootMode 2 See Table 14 SW1 4 BootMode 3 See Table 14 SW1 5 Factory Configuration Normal Operation SW1 6 XMC JTAG En...

Страница 13: ...D12 Red Status 1 See Status LED Definitions D16 Green Done FPGA is configured FPGA is unconfigured D2 Red PS Error PS error occurred No PS error D1 Green PS Status PS is in secure lockdown state PS i...

Страница 14: ...ed This is indicated by the Amber LED D9 The MVMRO signal has a 100K pull up resistor fitted by default This signal cannot be internally driven or over ridden A buffered version of the signal is conne...

Страница 15: ...scan chain is connected to the interface at the XMC connector SW1 X is ON Header U12 should not be used 3 3 2 XMC Interface The JTAG interface on the XMC connector is normally unused and XMC_TDI conne...

Страница 16: ...nterfaces FABRIC_CLK is used as the reference clock for the IO delay control block IDELAYCTRL Signal Frequency Target FPGA Input IO Standard P pin N pin REFCLK300M 300 MHz IO_L11_T1U_GC_66 LVDS AP11 A...

Страница 17: ...onitor PROGCLK 2 0 is generated by a dedicated programmable clock generator IC and offer extremely high frequency resolutions 1ppm increments PROGCLK 2 0 are all buffered copies of the same clock sign...

Страница 18: ...7 RF Sampling Clocks The RF reference clocks are generated with a dual loop jitter cleaner PLL The RF sampling clocks are provided by three LMX2594 RF clock synthesisers Figure 6 ADM XRC 9R1 RF sampli...

Страница 19: ...Sysref Clock Variable IO_L6_HDGC_88 G12 F12 RF Sysref Clock Variable SYSREF_228 N5 N4 Table 11 SysRef Connections 3 4 7 2 RF System FPGA Reference Clock The RF system FPGA reference clock is a differ...

Страница 20: ...AD4 ADC_CLK_225 AB5 AB4 ADC_CLK_226 Y5 Y4 ADC_CLK_227 V5 V4 DAC_CLK_228 L5 L4 DAC_CLK_229 J5 J4 FPGA 4 Wire Interface 2 bit Chip Select uWire SPI SPI SPI RF Power Supply Status Figure 7 CPLD Connectio...

Страница 21: ...gh all writes to the flash will be inhibited This state will be indicated by the Amber LED as shown in LED Locations 3 5 3 MicroSD Flash Memory A MicroSD card is used for storing executable code and d...

Страница 22: ...interface has three status LEDs The functions of these are shown in Table 15 below LED Colour Function 0 Green 1 Green 2 Amber Table 15 Ethernet Status LEDs 3 5 7 Serial COM Ports There are two seria...

Страница 23: ...faces connected to rear connector P4 The Zynq PS is configured as the USB host to the external interfaces The on board system monitor is accessible from the micro USB connector PS PHY ULPI Hub P4 USB1...

Страница 24: ...JTAG Boot Mode Select 89 3 3V PN6 GPIO 65 66 1 2V DRAM Banks 0 1 Table 16 Target FPGA IO Banks 3 6 2 MGT Links There are a total of 8 Multi Gigabit Transceiver MGT links connected to the Target FPGA...

Страница 25: ...nq RFSoC PL Bank 66 DRAM Bank 1 U36 DRAM Bank 0 U37 300MHz REFCLK Bank 65 Bank 65 Bank 66 Figure 12 PL DRAM Banks 3 6 4 GPIO There are 19 GPIO pins from the FPGA which are compatible with 3 3V signali...

Страница 26: ...SD over voltage protection to the FPGA inputs and have a maximum data rate of 210Mbps The DACs and ADCs use a MiniCircuits TCM2 43X 10 4000MHz transformer to convert the 100Ohm differential signal to...

Страница 27: ...2020 Signal Impedance Ohms J2 pin number DAC1 50 9 DAC2 50 8 DAC3 50 7 DAC4 50 6 DAC5 50 5 DAC6 50 4 DAC7 50 3 REF IN 50 2 REF OUT 50 1 EXTIO0 12 EXTIO1 11 Table 18 Front panel I O signals Page 21 Fun...

Страница 28: ...is de embedded using s parameters from this report http abconex es pdf Nicomatic 20HF 20Contacts 20High 20Speed 20Characterisation pdf For the DAC measurements the inverse SINC filter was OFF ADC meas...

Страница 29: ...ADM XRC 9R1 User Manual V1 7 16th Sept 2020 Figure 16 ADM XRC 9R1 DAC Performance Page 23 Functional Description ad ug 1353_v1_7 pdf...

Страница 30: ...algorithms within the microcontroller automatically check line voltages and on board temperatures and shares the information with the PS The following voltage rails and temperatures are monitored Mon...

Страница 31: ...ff and the two status LEDs showing a temperature fault indication The purpose of this mechanism is to protect the card from damage due to over temperature It is possible that it will cause the user ap...

Страница 32: ...Alpha Data utility called avr2util Avr2util is provided with the 9R1 PetaLinux BSP and can be run from the ADM XRC 9R1 once booted To see available options run avr2util To display sensor values use ps...

Страница 33: ...2V0 9 VPWR 10 GND GND TDO GND GND GA0 11 PER_P0 PER_N0 MBIST_L PER_P1 PER_N1 VPWR 12 GND GND GA1 GND GND MPRESENT_L 13 PER_P2 PER_N2 3V3_AUX PER_P3 PER_N3 VPWR 14 GND GND GA2 GND GND I2C_SDA 15 VPWR 1...

Страница 34: ...OM2_RXN 7 PN6_TX_P6 PN6_TX_N6 GP18 PN6_TX_P7 PN6_TX_N7 GND 8 GND GND GP17 GND GND ETH1_TX_P 9 GP16 ETH0_TX_P ETH0_TX_N ETH1_TX_N 10 GND GND GP15 GND GND GND 11 PN6_RX_P0 PN6_RX_N0 GP14 PN6_RX_P1 PN6_R...

Страница 35: ...89 GP7 F16 E9 89 GP8 C15 E10 89 GP9 MRSTO F15 K12 89 GP10 C14 C11 89 GP11 F14 C14 88 GP12 C13 D11 89 GP13 C12 E11 89 GP14 C11 A9 89 GP15 C10 B11 89 GP16 C9 B10 89 GP17 C8 C9 89 GP18 C7 D9 89 Table 25...

Страница 36: ...P4_ETH1_MDI_2_P P4_ETH1_MDI_0_N 15 16 P4_ETH1_MDI_2_N GND 17 18 GND P4_ETH1_MDI_1_P 19 20 P4_ETH1_MDI_3_P P4_ETH1_MDI_1_N 21 22 P4_ETH1_MDI_3_N GND 23 24 GND P4_USB1_DM 25 26 P4_USB2_DM P4_USB1_DP 27...

Страница 37: ...instead of P5 added details of PS Ethernet USB reference clocks updated GPIO information for new board revision added information about the RF transformers and front panel GPIO added more detail abou...

Страница 38: ...e Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales alpha data com website http www alpha data com Address 611 Corporate Circle Suite H Golden CO 80401 Telephone 3...

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