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ZYNQ FPGA Development Board AX7350B User Manual 

 

  28  /  46

 

 

 

Amazon Store: https://www.amazon.com/alinx 

 

PHY1_RESET 

PS_MIO7_500 

E23 

Reset signal 

 

PL-side Gigabit Ethernet pin assignments are as follows

：

 

Signal Name 

ZYNQ Pin Name 

ZYNQ Pin 

Number   

Description 

PHY2_TXCK 

IO_L4N_T0_35 

D11 

RGMII Transmit Clock 

PHY2_TXD0 

IO_L3N_T0_DQS_AD1N_35 

F10 

Transmit data bit0 

PHY2_TXD1 

IO_L3P_T0_DQS_AD1P_35 

G10 

Transmit data bit1 

PHY2_TXD2 

IO_L2N_T0_AD8N_35 

D10 

Transmit data bit2 

PHY2_TXD3 

IO_L2P_T0_AD8P_35 

E10 

Transmit data bit3 

PHY2_TXCTL 

IO_L4P_T0_35 

E11 

Transmit enable signal 

PHY2_RXCK 

IO_L11P_T1_SRCC_35 

G14 

RGMII Receive Clock 

PHY2_RXD0 

IO_L6P_T0_35 

F13 

Receive data Bit0

 

PHY2_RXD1 

IO_L1P_T0_AD0P_35 

F12 

Receive data Bit1 

PHY2_RXD2 

IO_L1N_T0_AD0N_35 

E12 

Receive data Bit2 

PHY2_RXD3 

IO_L5N_T0_AD9N_35 

G11 

Receive data Bit3 

PHY2_RXCTL 

IO_L6N_T0_VREF_35 

E13 

Receive data valid signal 

PHY2_MDC 

IO_0_VRN_35 

H16 

MDIO Management clock 

PHY2_MDIO 

IO_L7P_T1_AD2P_35 

H13 

MDIO Management data 

PHY2_RESET 

IO_L7N_T1_AD2N_35 

H12 

Reset signal 

Part 9: USB2.0 Host Interface 

There are 4 USB2.0 HOST interfaces on the AX7350B  FPGA 

development  board. The USB2.0 transceiver uses a 1.8V, high-speed 
USB3320C-EZK chip that supports the ULPI standard interface, and then 
expands the 4-way USB HOST interfaces through a USB HUB chip USB2514.   
ZYNQ's USB bus interface is connected to the USB3320C-EZK transceiver for 
high-speed USB2.0 Host mode data communication. The USB3320C's USB 
data and control signals are connected to the IO port of the BANK501 on the 
PS side of the ZYNQ chip. The USB interface differential signal (DP/DM) is 
connected to the USB2514  chip to extend the four USB ports. Two 24MHz 
crystals provide clocks for the USB3320C and USB2514 chips, respectively.   

Содержание ZYNQ7000 FPGA

Страница 1: ...ZYNQ7000 FPGA Development Board AX7350B User Manual...

Страница 2: ...ZYNQ FPGA Development Board AX7350B User Manual 2 46 Amazon Store https www amazon com alinx Version Record Revision Date Release By Description Rev 1 0 2019 04 05 Rachel Zhou First Release...

Страница 3: ...9 Part 6 Clock Configuration 20 Part 7 USB to Serial Port 24 Part 8 Gigabit Ethernet Interface 25 Part 9 USB2 0 Host Interface 28 Part 10 HDMI Output Interface 30 Part 11 SFP Interface 31 Part 12 PCIe...

Страница 4: ...erms of peripheral circuits we have extended a wealth of interfaces for users such as a PCIex4 slot 2 fiber interfaces 2 Gigabit Ethernet interfaces 4 USB2 0 HOST interfaces 1 HDMI output interface 1...

Страница 5: ...Q7350 chip two DDR3s are mounted each with a DDR3 capacity of up to 512 Mbytes The ARM system and the FPGA system can independently process and store data The PS side 8GB eMMC FLASH memory chip and 25...

Страница 6: ...igure 1 1 The Schematic Diagram of the AX7350B Through this diagram you can see the interfaces and functions that the AX7350B FPGA Development Board contains Xilinx ARM FPGA chip Zynq 7000 XC7Z035 2FF...

Страница 7: ...connected to the transmission and reception of two optical modules to realize two high speed optical fiber communication interfaces Each fiber optic data communication receives and transmits at speed...

Страница 8: ...nd file systems FMC expansion port A standard FMC LPC expansion port for connecting XILINX or ALINXDE various FMC modules HDMI input and output modules binocular camera modules high speed AD modules e...

Страница 9: ...s chip model XC7Z035 2FFG676 The chip s PS system integrates two ARM CortexTM A9 processors AMBA interconnects internal memory external memory interfaces and peripherals These peripherals mainly inclu...

Страница 10: ...Two USB2 0 OTG interfaces each supporting up to 12 nodes Two CAN2 0B bus interfaces Two SD card SDIO MMC compatible controllers 2 SPIs 2 UARTs 2 I2C interfaces 54 multi function IOs that can be confi...

Страница 11: ...azon Store https www amazon com alinx FGG676 pin pitch is 1 0mm the specific chip model definition of ZYNQ7000 series is shown in Figure 2 2 Figure 2 2 The Specific Chip Model Definition of ZYNQ7000 S...

Страница 12: ...terface of the BANK 502 of the ZYNQ Processing System PS The PL side DDR3 SDRAM has a maximum operating speed of 800MHz data rate 1600Mbps and two DDR3 memory systems are connected to the BANK33 and B...

Страница 13: ...igure 3 2 The Schematic Part of DDR3 DRAM on the PL side PS side DDR3 DRAM pin assignment Signal Name ZYNQ Pin Name ZYNQ Pin Number PS_DDR3_DQS0_P PS_DDR_DQS_P0_502 H24 PS_DDR3_DQS0_N PS_DDR_DQS_N0_50...

Страница 14: ...R_DQ11_502 K23 PS_DDR3_D12 PS_DDR_DQ12_502 M25 PS_DDR3_D13 PS_DDR_DQ13_502 N24 PS_DDR3_D14 PS_DDR_DQ14_502 M24 PS_DDR3_D15 PS_DDR_DQ15_502 N23 PS_DDR3_D16 PS_DDR_DQ16_502 R26 PS_DDR3_D17 PS_DDR_DQ17_5...

Страница 15: ..._A11 PS_DDR_A11_502 H21 PS_DDR3_A12 PS_DDR_A12_502 P20 PS_DDR3_A13 PS_DDR_A13_502 J20 PS_DDR3_A14 PS_DDR_A14_502 R20 PS_DDR3_BA0 PS_DDR_BA0_502 U22 PS_DDR3_BA1 PS_DDR_BA1_502 T22 PS_DDR3_BA2 PS_DDR_BA...

Страница 16: ...1 PL_DDR3_D8 IO_L7N_T1_33 H1 PL_DDR3_D9 IO_L10N_T1_33 G1 PL_DDR3_D10 IO_L7P_T1_33 J1 PL_DDR3_D11 IO_L8N_T1_33 H3 PL_DDR3_D12 IO_L11N_T1_SRCC_33 K3 PL_DDR3_D13 IO_L8P_T1_33 H4 PL_DDR3_D14 IO_L11P_T1_SR...

Страница 17: ...11N_T1_SRCC_34 E7 PL_DDR3_A7 IO_L15P_T2_DQS_34 C9 PL_DDR3_A8 IO_L12N_T1_MRCC_34 F7 PL_DDR3_A9 IO_L18N_T2_34 A7 PL_DDR3_A10 IO_L24N_T3_34 A2 PL_DDR3_A11 IO_L11P_T1_SRCC_34 F8 PL_DDR3_A12 IO_L23N_T3_34...

Страница 18: ...e FPGA bit files ARM application code and other user data files The specific models and related parameters of QSPI FLASH are shown in Table 4 1 Position Model Capacity Factory U10 W25Q256FVEI 32M Byte...

Страница 19: ...support of 1 8V or 3 3V The data width of the eMMC FLASH and ZYNQ connections is 4 bits Due to the large capacity and non volatile nature of eMMC FLASH it can be used as a large capacity storage devic...

Страница 20: ...MMC_D0 PS_MIO46_501 E17 MMC_D1 PS_MIO49_501 A18 MMC_D2 PS_MIO50_501 B22 MMC_D3 PS_MIO51_501 B20 Part 6 Clock Configuration The AX7350B FPGA development board provides a single ended active clock for...

Страница 21: ...nment Signal Name ZYNQ Pin PS_CLK B24 PL system clock source The AX7350B development board provides a single ended 50MHz PL system clock source with 1 8V supply The crystal output is connected to the...

Страница 22: ...6 4 50Mhz active crystal oscillator on the AX7350B board PL Clock pin assignment Signal Name ZYNQ Pin CLK_50MHZ J14 DDR Reference Clock A 200MHz differential crystal oscillator is provided to bank34 a...

Страница 23: ...sceiver In addition two channels of 100MHz differential reference clock are generated by the dsc557 0334fi1 chip and provided to the bank112 and PCIe socket respectively The schematic diagram of the r...

Страница 24: ...licon Labs CP2102GM The USB interface uses the MINI USB interface It can be connected to the USB port of the upper PC with a USB cable for separate power supply and serial data communication of the co...

Страница 25: ...erface of the PSNK501 of the PS side of ZYNQ The Ethernet PHY chip on the PL side is connected to the IO of the BANK35 The JL2121 chip supports 10 100 1000 Mbps network transmission rate and communica...

Страница 26: ...rk is connected to 100M Ethernet the data transmission of ZYNQ and PHY chip JL2121 is communicated through RMII bus and the transmission clock is 25Mhz Data is sampled on the rising edge and falling s...

Страница 27: ...RGMII Transmit Clock PHY1_TXD0 PS_MIO17_501 G17 Transmit data bit0 PHY1_TXD1 PS_MIO18_501 G20 Transmit data bit1 PHY1_TXD2 PS_MIO19_501 G19 Transmit data bit2 PHY1_TXD3 PS_MIO20_501 H19 Transmit data...

Страница 28: ...3 IO_L5N_T0_AD9N_35 G11 Receive data Bit3 PHY2_RXCTL IO_L6N_T0_VREF_35 E13 Receive data valid signal PHY2_MDC IO_0_VRN_35 H16 MDIO Management clock PHY2_MDIO IO_L7P_T1_AD2P_35 H13 MDIO Management data...

Страница 29: ...The connection between Zynq7000 and USB chip Figure 9 2 shows the physical diagram of the USB 2 0 chip and interface where the USB interface uses a dual USB interface USB2 0 Pin Assignment Signal Nam...

Страница 30: ...ected with the BANK35 IO of the ZYNQ7000 PL part The ZYNQ7000 system initializes and controls the ADV7511 through the I2C pin The hardware connection diagram of ADV7511 chip and ZYNQ7000 is shown in F...

Страница 31: ...nal data11 HDMI_D12 IO_L19P_T3_35 D13 HDMI Video signal data12 HDMI_D13 IO_L24N_T3_AD15N_35 A12 HDMI Video signal data13 HDMI_D14 IO_L19N_T3_VREF_35 C13 HDMI Video signal data14 HDMI_D15 IO_L24P_T3_AD...

Страница 32: ...reference clock for the BANK111 GTX transceiver is provided by 156 25Mhz Differential crystal oscillator Figure 11 1 detailed the FPGA and SFP schematic diagram ZYNQ SFP1_RX_N SFP1_RX_P SFP1 U1 SFP1_T...

Страница 33: ...dicates No optical signal received Part 12 PCIe Slot The AX7350B FPGA development board has a PCIe x8 slot that physically connects to the PCIe board In the electrical connection we only have 4 pairs...

Страница 34: ...eceive Negative PCIE_RX1_P Y4 PCIE Channel 1 Data Receive Positive PCIE_RX1_N Y3 PCIE Channel 1 Data Receive Negative PCIE_RX2_P V4 PCIE Channel 2 Data Receive Positive PCIE_RX2_N V3 PCIE Channel 2 Da...

Страница 35: ...access to the SD card memory the BOOT program for the ZYNQ chip the Linux operating system kernel the file system and other user data files The SDIO signal is connected to the IO signal of the PS BAN...

Страница 36: ...les binocular camera modules high speed AD modules etc The FMC expansion port contains 34 pairs of differential IO signals and one high speed GTX transceiver signal The 33 pairs of differential signal...

Страница 37: ...tion FMC_CLK0_P IO_L12P_T1_MRCC_12 AC13 FMC reference 1st channel reference clock P FMC_CLK0_N IO_L12N_T1_MRCC_12 AD13 FMC reference 1st channel reference clock N FMC_CLK1_P IO_L13P_T2_MRCC_13 AD20 FM...

Страница 38: ...reference 9th channel data P FMC_LA09_N IO_L10N_T1_12 AF13 FMC reference 9th channel data N FMC_LA10_P IO_L2P_T0_12 AB12 FMC reference 10th channel data P FMC_LA10_N IO_L2N_T0_12 AC11 FMC reference 1...

Страница 39: ...MC_LA25_P IO_L9P_T1_DQS_13 AB21 FMC reference 25th channel data P FMC_LA25_N IO_L9N_T1_DQS_13 AB22 FMC reference 25th channel data N FMC_LA26_P IO_L7P_T1_13 AE22 FMC reference 27th channel data P FMC_...

Страница 40: ...ur LED lights are connected to the IO of the PL The user can control the lighting and extinguishing through the program When the IO voltage connected to the user LED is low the user LED is off and whe...

Страница 41: ...al is connected to the PS reset pin of the ZYNQ chip The user can use this reset button to reset the ZYNQ system One of the five user buttons is connected to the IO of the PS and the other four button...

Страница 42: ...T0_34 J8 PL button 4 input Part17 JTAG Debug Port The AX7350B FPGA development board integrates the JTAG download debug circuitry so users do not need to purchase additional Xilinx downloader With a U...

Страница 43: ...hrough the DIP switch SW1 on the board The SW1 startup mode configuration is shown in Table 18 1 SW1 Switch Position 1 2 MIO5 MIO4 Level Start Mode ON ON 0 0 JTAG OFF OFF 1 1 SD Card OFF ON 1 0 QSPI F...

Страница 44: ...A1471FT 2G U59 MGTAVCC 3A ETA1471FT 2G U58 MGTAVTT 3A SPX3819M5 1 8 MGT_1 8V 0 6A VTT VREF U6 U9 TPS51200 Figure 19 1 Power interface section in the schematic The functions of each power distribution...

Страница 45: ...rt 20 Fan Because ZYNQ035 generates a lot of heat when it works normally we add a heat sink and fan to the chip on the board to prevent the chip from overheating The control of the fan is controlled b...

Страница 46: ...on Store https www amazon com alinx J22 The red is positive and the black is negative Figure 20 2 shows the physical diagram of the fan on AX7350B FPGA development board Figure 20 2 Fan on the AX7350B...

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