Alinco DR-138, Руководство по обслуживанию

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DR138
8
D/A
U505
U2
CPU
VCO
X200
TCXO
U205
PLL
2T/5T/DTMF
DCS/CTCSS
TCXO
MOD
VCO MOD
U504
FILTER
LPF
AFWN LPF
CPU
U503
U2
FILTER
BUFFER AMP
U501A
U2008
DTMF-DET
AMP
P02
P01
DTMF/2T/5T
DCS/CTCSS
COMPARATOR
CPU
U2
LCD
U3
LCD
COM0~COM3
SEG0~SEG39
driver
P85
P86
Q6,Q7
SW
8C
D5
P07
CIRCUIT DESCRIPTION
Fig. 12 Display circuit

Encode
CTCSS, DCS data of the P31 Line is output from pin 42 of the CPU. The signal passes through a
low-pass CR filter and goes to the D/A converter (U505).
High-speed data (2T/5T/DTMF) is output from pin 58 of the CPU. The signal passes through a low-pass
CR filter, providing TX and SP output audio frequency, and has processed IDC after amplified by a
U504(B/4). The signal then passes through a low-pass filter (separation filter) U504 (C/4 and D/4), and
filter the parts which are higher than 3kHz frequency, and the signal attained goes into the D/A converter
(U505).
The D/A converter (U505) adjusts the balance between the MOD and CTCSS/DCS levels. Signal of
CTCSS/DCS port is summed with MOD and the resulting signal goes to the VCO. This signal is applied to
a varicap diode in the VCO for direct FM modulation. (See Fig. 13.)
Fig. 13 Encode circuit

Decode
DCS/CTCSS/DTMF/2T/5T
The signal from (AFWN) entering into AF signal and higher audio frequencies output by pin 1 of U501: A
are cut by low-pass filter U503 and amplified. then led to pin 51 of CPU. The input signal is compared with
the programmed tone frequency code in the CPU. The squelch will open when they match.
The signal (DTMF-DET) goes to P02 (pin 52) of CPU (U2). The DTMF/2T/5T input signal from the
DTMF-DET goes to compared U2008. The compared signal goes to the CPU for processing and be
decoded within the CPU (U2). (See Fig. 14.)
Fig. 14 Decode circuit
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