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Aim AXC-FDX-2 Скачать руководство пользователя страница 17

3

.

Structure

of the AXC-FDX-2

AXC-FDX-2 Hardware Manual

9

3

STRUCTURE OF THE AXC-FDX-2

The structure of the AXC-FDX-2 board is shown in the block diagram on the next page.
The AXC-FDX-2 comprises the following main sections:



System on a Chip design with

-  Ethernet MAC
-  PCIe 2.0 Endpoint with DMA Engine
-  IRIG-B Synchronisation Unit
-  ASP Processor Core with Embedded Linux operating system
-  BIU Processor
-  Memory Interface



Physical IO-Interface

- Gigabit Ethernet PHY



Trigger IN / OUT



Discrete IO



QSPI Boot flash



I2C EEPROM

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Содержание AXC-FDX-2

Страница 1: ...V01 00 Rev A September 2017 AXC FDX 2 10 100 1000Mbit AFDX ARINC664 Test and Simulation XMC Interface Module Hardware Manual...

Страница 2: ......

Страница 3: ...AXC FDX 2 Hardware Manual i AXC FDX 2 10 100 1000Mbit AFDX ARINC664 Test and Simulation XMC Interface Module V01 00 Rev A September 2017 AIM No 60 15A40 16 0100 A Hardware Manual...

Страница 4: ...nline com AIM GmbH Munich Sales Office Terofalstr 23a D 80689 M nchen Germany Phone 49 0 89 70 92 92 92 Fax 49 0 89 70 92 92 94 salesgermany aim online com AIM USA LLC Seven Neshaminy Interplex Suite...

Страница 5: ...AXC FDX 2 Hardware Manual iii DOCUMENT HISTORY The following table defines the history of this document Version Cover Date Created by Description 01 00 Rev A 13 09 2017 Marco Maier First Release...

Страница 6: ...AXC FDX 2 Hardware Manual iv THIS PAGE IS INTENTIONALLY LEFT BLANK...

Страница 7: ...er Discrete and IRIG Connector 5 2 3 3 AXC FDX 2 Rear I O Interface 7 3 Structure of the AXC FDX 2 9 3 1 System on Chip SoC 11 3 1 1 Ethernet MAC Features 11 3 1 2 PCI Express Bus and DMA Engine 11 3...

Страница 8: ...X 2 4 Figure 2 3 Pinout DSUB 5 Figure 3 1 AXC FDX 2 Block Diagram 10 Figure 3 2 GPI O AXC FDX 2 circuitry 15 Figure 3 3 Discrete Protection with external resistor 16 LIST OF TABLES Table Title Page Ta...

Страница 9: ...t timing The receivers feature multiple error detection time tagging of each received frame with 100ns resolution inter frame gap measurement with up to 40ns resolution 1000Mbit 8ns and statistic feat...

Страница 10: ...FDX 2 1 3 Applicable Documents The following documents shall be considered to be a part of this document to the extent that they are referenced herein In the event of conflict between the documents r...

Страница 11: ...ed may result in damage to module devices 3 Touch a metal plate on your system to ground yourself and discharge any static electricity 4 Remove the carrier board from the system slot 5 Replace the XMC...

Страница 12: ...erfaces of the AXC FDX 2 consist of two RJ45 Ethernet connectors Trigger In Out signal Discrete IO signals Ground as well as IRIG In Out interface for multi channel time tag synchronization Figure 2 2...

Страница 13: ...up to 4 users definable Discrete I Os are placed on the connector This connector is implemented by a 3 row 15pin female HD SUB Connector Technical Details about the Trigger and Discrete lines can be f...

Страница 14: ...e AIM Modules with no common synchronization requirement No connection required 3 Single or multiple AIM Module s with external IRIG B source Connect external IRIG B source to IRIG IN and GND of all m...

Страница 15: ...GND 10 11 Signal GND Signal GND 12 13 Reserved Reserved 14 15 Signal GND Reserved 16 17 Signal GND Reserved 18 19 Reserved Reserved 20 21 IRIG OUT Reserved 22 23 IRIG IN Reserved 24 25 Discrete IO1 D...

Страница 16: ...2 Instalation AXC FDX 2 Hardware Manual 8 THIS PAGE INTENTIONALLY LEFT BLANK...

Страница 17: ...the next page The AXC FDX 2 comprises the following main sections System on a Chip design with Ethernet MAC PCIe 2 0 Endpoint with DMA Engine IRIG B Synchronisation Unit ASP Processor Core with Embed...

Страница 18: ...J45 Transformer RJ45 Transformer Host XMC connector PCIe Endpoint 1 GB Processor RAM PS Dual Core PCIe 2 0 x1 Z015 Quartz Clock Buffer IRIG Maintenance Connector DMA Data Handler NAND QSPI Boot Flash...

Страница 19: ...s checked for errors in the MAC header and the IP header and for errors on the physical bus The transmitter operates fully independent from the receiver The transmitter is capable of generating data i...

Страница 20: ...ed The time code information can be used for time tagging and multi channel synchronization 3 1 3 2 Timecode Encoder Decoder On the AXC FDX 2 a freewheeling IRIG function is implemented If no external...

Страница 21: ...ng and Analysis of received data Support special transmit modes like redundant transmit or Simulation mode 3 1 6 Memory Interface The SoC has a dedicated 1GByte DDR3 RAM directly attached to it storin...

Страница 22: ...ge level is of type TTL and is 5 0V tolerant Varistors on the Front IO are placed nearby connector to suppress peaks of glitches ESD sparks 3 4 User programmable Discrete I O The AXC FDX 2 module prov...

Страница 23: ...rrent through the open collector transistor to maximum current see technical data chapter for details Otherwise the open collector transistor can be damaged EMC aspects are covered by filter circuitry...

Страница 24: ...AXC FDX 2 AXC FDX 2 Hardware Manual 16 Figure 3 3 Discrete Protection with external resistor Discrete IO Pin Front Connector Off Board User Voltage Customized Discrete Output Rserial AXC FDX 2 Board G...

Страница 25: ...coders with error injection Data rate of 10 100 1000 Mbit per second Interframe Gap timer with 8ns resolution at 1000Mbit 40ns resolution at 100Mbit 400ns resolution at 10Mbit Error injection CRC Erro...

Страница 26: ...IG B 122 Absolute Accuracy 25ppm standard Oscillator Signal Waveform Amplitude modulated sine wave Output Amplitude 4 5 Vp p High voltage level Output Impedance 51 ohm Coupling AC coupled Modulation R...

Страница 27: ...aximum Sink Current of each open collector 50 mA Please note When the default 5V for the discrete outputs are not used provide a serial resistor in line with the open collector transistor If using a d...

Страница 28: ...4 Technical Data AXC FDX 2 Hardware Manual 20 THIS PAGE IS INTENTIONALLY LEFT BLANK...

Страница 29: ...Range Instrumentations Group Time code Format Type B I O Input Output JTAG Joint Test Action Group IEEE 1149 1 Boundary Scan LCA Logic Cell Array Field Programmable Logic LED Light Emitting Diode MDI...

Страница 30: ...5 NOTES AXC FDX 2 Hardware Manual 22 THIS PAGE IS INTENTIONALLY LEFT BLANK...

Страница 31: ...Modifiable Yes No Function LINUX Program Data Firmware FPGA Boot Process to Sanitize Erase Type Serial SPI Flash Size 128Mbit User Modifiable Yes No Type Serial I C Bus EEPROM Size 8kbit User Modifiab...

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