Aim APE1553-1-DS, Руководство по оборудованию

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APE1553-1/2(-DS) Hardware Manual
1
1 INTRODUCTION
1.1 General
This document comprises the Hardware User’s Manual for the APE1553-1 and
APE1553-2 PCIe-Modules.
This document covers the hardware installation, the board connections the technical
data and a general description of the hardware architecture. For programming
information please refer to the documents listed in the ‘Applicable Documents’ section.
The APE1553 modules are members of AIM's new family of advanced PCI Express
cards compliant to PCI Express V1.1. The PCI Express Interface is 1-lane wide and
working with 2.5 Gbit/s in transmit and receive direction.
The APE1553 modules are used to simulate, monitor and inject protocol errors of MIL-
STD-1553A/B based databus systems. The APE1553-1/-2 offers an interface for up to
two dual-redundant MIL-STD-1553 bus channels. Furthermore the interface implements
trigger IN/OUT functions for Bus Controller (BC), Remote Terminal (RT) and Bus
Monitor (BM), as well as 8 user programmable Discrete I/O signals. An additional free
wheeling IRIG-B time code generator allows the user to synchronize to either the
onboard generated time code or the time code of an external board with a resolution of
1us.
Transformer-, Direct-, Network Emulation- and Isolated-Coupling Modes are available
at the external interface connector. A standard breakout cable (2.0 m) is available for
the APE1553 card from DSUB9 connector to four (two, if APE1553-1 module) PL-75
Twinax Connectors.
The hardware architecture provides enough resources (i.e. processing capability and
memory) to guarantee, that all specified interface functions are available concurrently
and to full performance specifications.
A powerful PCI-Express Controller and Memory Arbiter is implemented in a Field
Programmable Gate Array (FPGA). This FPGA supports both, the interface to the
application and driver software tasks running on the host computer and assists the
communication for data transfer.
This feature expands the capability of the APE1553 module to that of a high level
instrument. To fulfil the real-time requirements of a typical avionic type databus system,
a high performance 32bit RISC processor (BIP) is implemented for each Bus Interface
Unit (BIU) / each MIL-STD-1553A/B stream.
A free wheeling IRIG-B Time code Encoder/Decoder is implemented on the APE1553
to satisfy the requirements of 'multi-channel time tag synchronization' on the system
level. The IRIG-B compatible amplitude modulated sinewave output allows the
synchronization of any external module implementing IRIG-B time stamping.