Aim APE1553-1-DS, Руководство по оборудованию

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APE1553-1/2(-DS) Hardware Manual
3.2 Global RAM
The Global RAM is shared between both BIU processors (BIP) and the Host PCIe-Bus.
The arbitration is handled by the common FPGA. It has access to the common Global
RAM via a 32 bit wide data port.
3.3 BIU Section
Up to two Bus Interface Units (BIUs) are implemented on the module using low power,
high performance 32bit RISC processors.
Each BIU handles one MILbus-Channel and generates the Trigger-Signals.
3.4 Physical Bus Interface with two Dual Redundant MIL-STD-1553B Channels
The Physical Bus Interface (PBI) is implemented as a daughter-board and is mounted
on the APE1553 main board. The Physical Bus Interface (PBI) contains one or two dual
redundant MIL-STD-1553 channels, each channel comprises a dual-redundant
transceiver, transmitter amplitude control circuitry, a dual bus coupling transformer and
the coupling relays with the MILbus network emulation circuitry.
The MIL-STD-1553 dual trapezoidal transceivers allow for output amplitude control on
primary and secondary channel.
The MILbus coupling network of the PBI consists of sophisticated relay circuitry which
offers various coupling capabilities.
The following coupling modes can be programmed by the software:
•
Transformer coupled
•
Direct coupled
•
Transformer coupled with resistive network emulation
•
Isolated (Internal termination)