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8. Technical Data
ANET1553-x
User’s Manual
47
8
TECHNICAL DATA
Memory : DDR2 RAM (Global RAM)
- 128MByte
LPDDR RAM (ASP Local RAM)
- 256MByte
SPI-Flash for FPGA Boot
- 8MByte
SPI-Flash for BIU Processor
- 1MByte
NAND Flash for ASP Processor
- 1GByte
BIU-Section: Low power, high performance 32bit RISC Processor;
core voltage 1.0V, core speed 400 MHz, ext. bus speed 100MHz,
Encoder For each BIU, one Manchester Encoder with Parity generator and
error injection
Single implementation with bus switching logic (not redundant)
Response time support via eight bit timer with 250ns resolution
Error Injection Parity error on selected word
SYNC pattern definable on half bit basis on selectable word
Manchester stuck at low or high error in selected word and bit
position
Gap error between selected words for 0.5 to 7.5 µs in 0.5µs steps
Bit count error on selected word +/- 3 bits
Parity error on selected word
Decoder For each BIU, one Manchester Decoder with Parity checker and
error detection.
Single implementation with bus switching logic (not redundant).
Full error detection and indication
inter word gap timer with 250ns resolution (nine bit).
Time Tagging:
IRIG-B Time Tag For absolute time tagging, a special time code processor
implements an IRIG-B-122 encoder/decoder. If no external IRIG
source is available a time code in IRIG-B-122 format is generated
and can be used to synchronize multiple boards or modules.
Decoder
Format IRIG-B-122
Resolution: 1 µs
Width: 1 Year (46 Bit)
Signal Waveform: Amplitude modulated sine wave or square wave
Modulation Ratio: 3:1 to 6:1
Input Amplitude: 0.6V
p-p
to 5V
p-p