Aim ANET1553 Series, Руководство пользователя

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4. Structure of the ANET1553
ANET1553-x
User’s Manual
32
4.1 System FPGA
The System FPGA includes the ASP processor Interface logic, the Interface Logic for
the BIU processor and the MIL-STD-1553 Encoder / Decoder Logic.
The following features are implemented in the System FPGA:

Global RAM interface and arbitration

SPI controller for updating the on board SPI-Flashes

MIL-STD-1553 Encoder / Decoder

IRIG-B Logic

Time Code Processor Function

µMon-Software

Trigger-I/O Logic

Discrete-I/O Logic

ASP & BIU processor Interface
4.2 Global RAM
128MByte RAM, shared between the ASP-, BIU-Processor and the FPGA internal
Microcontroller.
4.3 BIU Section
The BIU consist of the BIU processor, the MIL-STD-1553 Encoder/Decoder logic to
handle up to two MIL-STD-1553 channels, the Trigger-Logic to handle the Trigger-I/O
signals in BC, RT and BM operating modes and a SPI-Flash for BIU-Processor Boot, all
implemented in the FPGA.
4.3.1 MIL-STD-1553 Encoder
The MIL-STD-1553 encoder comprises a Manchester Encoder with full error injection
capability as required by the 'Remote Terminal Production Test Plan'.
4.3.2 MIL-STD-1553 Decoder
The MIL-STD-1553 Manchester decoder samples the incoming serial data stream.
The decoder detects the synchronization pattern (Command/Status and Data Sync.),
converts 16 bit Manchester encoded serial data to parallel and receives the parity bit.
The decoder indicates the synchronization pattern and error information (parity error,
Manchester error, framing error) via dedicated bits in an error status register.