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ACE1553-3U-4 Hardware Manual

9

and receives the parity bit. The decoder indicates the sync. pattern and error information (parity
error, Manchester error, framing error) via dedicated bits in a readable error register.

3.1.6 IRIG-B Encoder/Decoder and Timecode Processor (TCP)

The  IRIG-B  time  code  will  be  received  and  decoded  from  the  TCP.  The  decoded  millisecond
time  code  received  from  TCP  is  expanded  by  a  self-generated  microsecond  value  and
organized to a 46Bit time tag value.
The IRIG-B time encoder generates the transmitted timecode sinusoidal signal. The IRIG start-
time can be set via software.

3.1.7 System & Maintenance Controller / RS232 Maintenance Interface

The System and Maintenance Controller is used for on board debugging and board
maintenance purposes in the factory.

3.1.8 External Trigger Inputs and Outputs

For  Bus  Controller  (BC),  Remote  Terminal  (RT)  and  Bus  Monitor  (BM)  triggering,  separate
trigger input and trigger output are provided for each MILbus channel at the Front I/O connector.
The  minimum  trigger  pulse  length  must  be  greater  than  75  nanoseconds  to  be  detected.  The
trigger inputs are high active and their voltage level is of type TTL and is +5.0V tolerant.

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Содержание ACE1553-3U-4

Страница 1: ...Hardware Manual V01 10 Rev A January 2016 ACE1553 3U 4 Quad Stream MIL STD 1553 PXI Express cPCI Express 3U Modules ...

Страница 2: ......

Страница 3: ...ACE1553 3U 4 Hardware Manual i ACE1553 3U 4 Quad Stream MIL STD 1553 PXI Express cPCI Express 3U Modules V01 10 Rev A January 2016 AIM No 60 117E0 16 0110 A Hardware Manual ...

Страница 4: ... online com AIM GmbH Munich Sales Office Terofalstr 23a D 80689 München Germany Phone 49 0 89 70 92 92 92 Fax 49 0 89 70 92 92 94 salesgermany aim online com AIM USA LLC Seven Neshaminy Interplex Suite 211 Trevose PA 19053 Phone 267 982 2600 Fax 215 645 1580 salesusa aim online com AIM GmbH 2015 Notice The information that is provided in this document is believed to be accurate No responsibility i...

Страница 5: ...ORY The following table defines the history of this document Version Cover Date Created by Description V01 00 Rev A 10 06 2015 E Carraro First Released Version V01 10 Rev A 19 01 2016 E Carraro New layout corrections on the discrete section CDR5898 ...

Страница 6: ...ACE1553 3U 4 Hardware Manual iv THIS PAGE IS INTENTIONALLY LEFT BLANK ...

Страница 7: ... 3 Controller for SPI Flash update programming 8 3 1 4 MIL STD 1553 Encoder 8 3 1 5 MIL STD 1553 Decoder 8 3 1 6 IRIG B Encoder Decoder and Timecode Processor TCP 9 3 1 7 System Maintenance Controller RS232 Maintenance Interface 9 3 1 8 External Trigger Inputs and Outputs 9 3 1 9 User programmable Discrete I O GPIO 10 Global RAM 11 3 2 BIU Section 11 3 3 Physical Bus Interface with four Dual Redun...

Страница 8: ...4 connector s pin out 15 Table 3 4 PXIe XJ3 connector s pin out 15 LIST OF FIGURES Figure Title Page Figure 2 1 Front Panel View 4 Figure 2 2 Pinout of the 15 Pin HD DSUB connector 5 Figure 2 3 Status LED view 6 Figure 3 1 Block Diagram of ACE1553 3U 4 7 Figure 3 2 GPI O ACE 1553 3U x circuitry 10 Figure 3 3 GPIO Protection with external resistor 11 Figure 3 4 MILbus Amplitude vs Vcontrol 13 Figur...

Страница 9: ...e external interface connector A standard breakout cable 2 0 m is available for the ACE1553 card from HD DSUB15 connector to four two if ACE1553 3U 1 module PL 75 Twinax Connectors The hardware architecture provides enough resources i e processing capability and memory to guarantee that all specified interface functions are available concurrently and to full performance specifications A powerful P...

Страница 10: ... of the ACE1553 Applicable Documents 1 3 The following documents shall be considered to be a part of this document to the extent that they are referenced herein In the event of conflict between the documents referenced and the contents of this document the contents of this document shall have precedence 1 3 1 Industry Documents 1 PXI Express Hardware Specification Rev 1 0 Aug 22 2005 2 PXI Hardwar...

Страница 11: ...er cord from the wall outlet Inserting or removing modules with power applied may result in damage to module devices 3 Find a free peripheral hybrid expansion slot in your system 4 Remove the slot bracket from the slot you have chosen and put it aside 5 Make sure the injector ejector handle is in its downward position 6 Align the ACE1553 with the card guides on the top and bottom of the peripheral...

Страница 12: ...th MIL STD 1553A B Trigger In Out signals for Bus Monitor Bus Controller and Remote Terminals as well as the IRIG IN OUT interface for multi channel time tag synchronization Figure 2 1 Front Panel View The ACE1553 3U 4 interface comprises two female DSUB15 connectors which providing the MILbus signals the Trigger IN OUT the GPIOs and the IRIG IN OUT signals ...

Страница 13: ...igger CH3 OUT 9 Trigger CH2 IN 9 Trigger CH4 IN 10 Trigger CH2 OUT Trigger CH4 OUT 11 MILBus Channel 2 A true MILBus Channel 4 A true 12 MILBus Channel 2 A compl MILBus Channel 4 A compl 13 GND GND 14 MILBus Channel 2 B true MILBus Channel 4 B true 15 MILBus Channel 2 B compl MILBus Channel 4 B compl Table 2 1 Pin Description of the two HD DSUB15 front panel connectors 2 3 2 General Purpose I O Co...

Страница 14: ...f test occurs BUSY CH2 Green LED illuminates permanently if the MILbus channel 2 is connected LED flashes if any MILbus Activity is detected by the Encoder Decoder of the MILbus channel 2 FAIL CH3 Red LED illuminates if an Error during the MILbus Channel3 self test occurs BUSY CH3 Green LED illuminates permanently if the MILbus channel 3 is connected LED flashes if any MILbus Activity is detected ...

Страница 15: ... 3U 4 comprises the following main sections PCI Express bus and BIU IO FPGA Global RAM BIU Processor Section Physical I O Interface with up to four Dual redundant MIL STD 1553B Channels IRIG Time Code Proc with free wheeling function and Sine Wave Output Boot Up Flash PXI Instrumentation Bus Figure 3 1 Block Diagram of ACE1553 3U 4 ...

Страница 16: ...ols Global RAM access between the participants BIU Processors PCIe and the Timecode Processor in a fair arbitration scheme 3 1 2 Boot Function To provide maximum flexibility and upgradeability the FPGA device and the processor are booted automatically after power up 3 1 3 Controller for SPI Flash update programming IP Core SPI Controller to program the on board SPI Flash memory 3 1 4 MIL STD 1553 ...

Страница 17: ...time encoder generates the transmitted timecode sinusoidal signal The IRIG start time can be set via software 3 1 7 System Maintenance Controller RS232 Maintenance Interface The System and Maintenance Controller is used for on board debugging and board maintenance purposes in the factory 3 1 8 External Trigger Inputs and Outputs For Bus Controller BC Remote Terminal RT and Bus Monitor BM triggerin...

Страница 18: ...d make sure that the output mode for that discrete is disabled before connecting an external voltage otherwise a high short circuit current to GND can damage the output transistor Figure 3 2 GPI O ACE 1553 3U x circuitry Be aware that a series resistor must be provided when a user voltage is used Figure 3 3 This serial resistor must limit the current through the open collector transistor to max cu...

Страница 19: ... a 32 bit wide data port BIU Section 3 3 Up to two Bus Interface Units BIUs are implemented on the ACE1553 3U module Both BIUs implement exactly the same functionality Each BIU handle up to two MIL STD 1553B channels and provide the trigger signals for BC RT and BM applications The control logic is implemented in the common FPGA device Discrete IO Pin Front Connector Off Board User Voltage Customi...

Страница 20: ...ceivers allow for output amplitude control on primary and secondary channel The MILbus coupling network of the PBI consists of sophisticated relay circuitry which offers various coupling capabilities The following coupling modes shown in Table 3 1 can be programmed via software Transformer coupled Direct coupled Transformer coupled with resistive network emulation Isolated Internal termination MIL...

Страница 21: ...Vcontrol input which can be derived from the following formula 256 2 N V V ref B outA Where N is the 8 bit digital input value and Vref the voltage on the Reference pin The input value in this formula is the digital 8 bit value 0 255 written to the onboard digital to analogue converters The 100 value depends on the transceiver type the coupling mode and the bus termination The output value is appr...

Страница 22: ... IRIG B signal The time tag on the board is generated in the format explained in the following table Time Element Number of bits DAYS of Year 9 HOURS of Day 5 MINUTES of Hour 6 SECONDS of Minute 6 MICROSECONDS of Second 20 Summary 46 6 Bytes stored in two 32bit words Table 3 2 IRIG B Binary Coded Time Tag 3 5 2 Time Tag Methods The IRIG IN and IRIG OUT signals shall be connected depending on the T...

Страница 23: ... GA0 GND 2 GND 5VAUX GND RSV RSV RSV GND 3 GND 12V 12V GND GND GND GND 4 GND GND GND 3 3V 3 3V 3 3V GND 5 GND PXI_TRIG_3 PXI_TRIG_4 PXI_TRIG_5 GND PXI_TRIG_6 GND 6 GND PXI_TRIG_2 GND RSV PXI_STAR PXI_CLK10 GND 7 GND PXI_TRIG_1 PXI_TRIG_0 RSV GND PXI_TRIG_7 GND 8 GND RSV GND RSV PXI_LBL6 PXI_LBR6 GND Table 3 3 PXIe XJ4 connector s pin out XJ3 Connector pin A B ab C D cd E F ef 1 RSV RSV GND RSV RSV...

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Страница 25: ...reserving compatibility with current PXI modules users benefit from increasing bandwidth while maintaining backward compatibility with existing systems PXIe specifies PXIe hybrid slots to deliver signals for both PCI and PCIe Figure 4 1 PXI architecture PXIe combines industry standard PC components such as the PCI Express bus with advanced triggering and synchronization extensions on the backplane...

Страница 26: ...any of the newer controllers The ACE1553 3U 4 card can route its Trigger INPUTs and or Trigger OUTPUTs to the PXI backplane trigger lines letting the user to deliver receive trigger signals to from other PXI cards present in the system a Trigger Controller another AIM PXI capable product Each Trigger Line can be assigned to any BC RT or BM Trigger Input or Trigger Output to use the advantage of al...

Страница 27: ...ACE1553 3U 4 Hardware Manual 19 Figure 4 2 PXI Front Panel PBI Trigger Routing capabilities ...

Страница 28: ...ed among boards they have a higher skew typically nanoseconds versus picoseconds than the chassis clock and the signals are not shielded The PXI system clock is able to maintain its quality by using a low skew fan out buffer chip that essentially provides a unique clock for every slot Furthermore because the clock lines are built into the backplane the lines are better shielded than external lines...

Страница 29: ...e placed in Slot 2 of the chassis Slot 2 is dedicated for the star trigger controller although any standard module placed in Slot 2 will function normally in an application where star triggering is not required Receiving modules must also be designed to be able to accept the star trigger The standard PXI trigger bus can perform the same functionality with a trigger signal from any chassis slot but...

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Страница 31: ...IU one Manchester Encoder with Parity generator and error injection Single implementation with bus switching logic not redundant Response time support via eight bit timer with 250ns resolution Error Injection Parity error on selected word SYNC pattern definable on half bit basis on selectable word Manchester stuck at low or high error in selected word and bit position Gap error between selected wo...

Страница 32: ...ments an IRIG B encoder decoder If no external IRIG B source is available a time code in IRIG B format is generated and can be used to synchronize multiple boards or modules Decoder Resolution 1 µs Width 1 Year 46 Bit Signal Waveform Amplitude modulated sine wave or square wave Modulation Ratio 3 1 to 6 1 Input Amplitude 0 5Vp p to 5Vp p Input Impedance 10k ohm Coupling AC coupled Time Jitter 5µs ...

Страница 33: ...ct coupled stub connections Emulates a 70 Ω transformer coupled network stub if programmed accordingly Trigger In TTL compatible Input Level 10K Pull Up resistor and high speed EMV varistor Rising Edge sensitive Pulse width 75 ns Trigger Out Output with TTL Level with high speed EMV varistor High Pulsewidth strobe 500 ns duration PXI Trigger Bus STAR Clock All PXI Inputs are TTL Level compatible A...

Страница 34: ...e open collector transistor If using a discrete pin as input make sure that the output mode is set to default before connecting an external voltage Otherwise the transistor can be damaged Paragraph 3 1 9 Supply Voltage Standard cPCIe Supply 3 3V 12 0V Dimensions PXI PXIe slot compatible 100 x 160 mm Power Consumption ACE1553 3U 4 Working 1 idle 3 3V 2 60 W 2 55 W 12 0V 11 50 W 3 15 W Note 1 all ch...

Страница 35: ...RIG B Inter Range Instrumentations Group Time code Format Type B I O Input Output JTAG Joint Test Action Group IEEE 1149 1 Boundary Scan LCA Logic Cell Array Field Programmable Logic N A Not Applicable NC Not Connected PC Personal Computer PCB Printed Circuit Board PROM Programmable Read Only Memory PCI Peripheral component interconnect PCIe Peripheral component interconnect Express PBI Physical B...

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