Agilent Technologies N8900 series, Руководство по эксплуатации

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Status Tutorial
Bit Bit Name
Decimal
Value
Definition
5
Event Status
Summary
32
One or more bits are set in the Standard Event Register. Bits
must be enabled, see
*ESE .
6
Master Status
Summary
64
One or more bits are set in the Status Byte Register and may
generate a Service Request. Bits must be enabled, see
*SRE .
7
Operation Status
Summary
128
One or more bits are set in the Operation Status Register. Bits
must be enabled, see
STATus:OPERation:ENABle .
MSS and RQS Bits
MSS is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service Request Enable
register. MSS is set whenever the instrument has one or more reasons for requesting service. *STB? reads the MSS in
bit position 6 of the response but does not clear any of the bits in the Status Byte register.
The RQS bit is a latched version of the MSS bit. Whenever the instrument requests service, it sets the SRQ interrupt
line true and latches RQS into bit 6 of the Status Byte register. When the controller does a serial poll, RQS is cleared
inside the register and returned in bit position 6 of the response. The remaining bits of the Status Byte register are not
disturbed.
Error and Output Queues
The Error Queue is a first-in, first-out (FIFO) data register that stores numerical and textual description of an error or
event. Error messages are stored until they are read with
SYSTem:ERRor? If the queue overflows, the last error/event
in the queue is replaced with error -350,"Queue overflow".
The Output Queue is a first-in, first-out (FIFO) data register that stores instrument-to-controller messages until the
controller reads them. Whenever the queue holds messages, it sets the MAV bit (4) of the Status Byte register.
102 Agilent N8900 Series Operating and Service Guide