Agilent Technologies J-BERT N4903, Руководство пользователя

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How does Clock Data Recovery Work?
In CDR mode, the CDR has to recover the clock from the incoming data.
To do this, the hardware has to decide whether the voltage at the input
connector is a logical '1' or '0' and then recover the clock from the
detected transitions.
Clock Data Recovery (CDR) is a special kind of Phase Locked Loop
(PLL), which recovers clock signal from of a data stream. It is a
regulatory loop, which synchronizes the local oscillator with an external
reference, in this case the incoming data stream.
Phase Locked Loop
A PLL has three parts: a phase detector, a loop filter, and a voltage
controlled oscillator (VCO). The phase detector has two inputs, and one
output, which is proportional to the phase difference of the inputs. The
loop filter is a low pass filter which attenuates the higher frequencies
from the output of the phase detector. The VCO is an adjustable
oscillator which changes the output frequency depending on its input
voltage. The diagram below shows a simple PLL.
One of the most important characteristics of a PLL is its loop transfer
function.The loop bandwidth is defined as the integrated magnitude of
the PLL’s frequency transfer function over the entire frequency
spectrum. The loop bandwidth describes how the regulatory loop tracks
the VCO to a sine wave FM modulated input signal. Above the bandwidth
the loop cannot track such a modulation completely, and thus, the
response to the modulation is attenuated.
The other loop parameter is peaking. This describes how much a
modulation is exaggerated (mostly close to the loop bandwidth).
Setting up the Error Detector
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Agilent J-BERT N4903 High-Performance Serial BERT 117