Chapter 2
41
E4438C Vector Signal Generator Overview
Rear Panel Overview
output on the EVENT 1 connector occurs whenever Marker 1 is turned on in the waveform.The output on
the EVENT 2 connector occurs whenever Marker 2 is turned on in the waveform. (Markers are
automatically turned on whenever you set them in a waveform segment. When you combine waveform
segments that contain Marker 2 into a sequence, the markers are automatically turned off until you toggle
them on in either the Edit Selected Waveform Sequence menu or in the Build New Waveform Sequence
menu.)
The damage levels are > +8 V and <
−
4 V. On signal generators with Option 1EM, this output is changed
from a BNC to an SMB connector. With Option 401 this connector is used for system reset output.
12. PATT TRIG IN Connector (Option 001/601 or 002/602)
This female BNC input connector can accept either a CMOS low to CMOS high, or CMOS high to CMOS
low edge trigger. The minimum trigger input pulse width, high or low, is 100 ns. The damage levels are
> +5.5 volts and <
−
0.5 volts. If you configure your signal generator with Option 1EM, this input is
changed from a BNC to an SMB connector.
The input to the PATT TRIG IN connector is used to trigger the internal digital modulation pattern generator
to start a single pattern output or to stop and re-synchronize a pattern that is being continuously output. The
trigger edge is latched and then sampled by the falling edge of the internal data bit clock to synchronize the
trigger with the data bit clock timing. The minimum delay from the trigger edge to the first bit of the frame
is 1.5 to 2.5 bit clock periods.
This connector is the source for the external trigger for all of the ARB waveform generator triggers. With
Option 401, this connector is used for even second synchronization input.
13. AUX I/O Connector
This female 37-pin connector is active only on instruments with an internal baseband generator (Option
001/601or 002/602); on signal generators without one of these options, this connector is non-functional.
This connector provides access to the inputs and outputs described in the following table and shown in
Connector Pin
Description
ALT PWR IN
Pin-16 of the Aux I/O connector is used with an internal baseband generator. This pin
accepts a CMOS signal for synchronization of external data and alternate power signal
timing. Damage levels are > +5.5 volts and <
−0.5
volts.
DATA CLK OUT
Pin-6 of the Aux I/O connector is used with an internal baseband generator. This pin
relays a CMOS bit clock signal for synchronizing serial data. Damage levels are >
+5.5 volts and <
−0.5
volts.
DATA OUT
Pin-7 of the Aux I/O connector is used with an internal baseband generator. This pin
outputs data (CMOS) from the internal data generator or the externally supplied signal at
data input. Damage levels are > +5.5 volts and <
−0.5
volts.
Содержание E4428C
Страница 22: ...Contents xxii ...
Страница 107: ...Chapter 3 83 Basic Operation Using Security Functions Figure 3 6 ESG Screen with Secure Display Activated ...
Страница 182: ...158 Chapter 4 Basic Digital Operation Using Waveform Clipping Figure 4 22 Rectangular Clipping ...
Страница 183: ...Chapter 4 159 Basic Digital Operation Using Waveform Clipping Figure 4 23 Reduction of Peak to Average Power ...
Страница 224: ...200 Chapter 4 Basic Digital Operation Creating and Using Bit Files ...
Страница 228: ...204 Chapter 5 AWGN Waveform Generator Configuring the AWGN Generator ...
Страница 229: ...205 6 Analog Modulation ...
Страница 276: ...252 Chapter 7 Digital Signal Interface Module Operating the N5102A Module in Input Mode ...
Страница 286: ...262 Chapter 8 Bluetooth Signals Turning On a Bluetooth Signal ...
Страница 287: ...263 9 BERT This feature is available only in E4438C ESG Vector Signal Generators with Option 001 601or 002 602 ...
Страница 330: ...306 Chapter 9 BERT Verifying BERT Operation ...
Страница 366: ...342 Chapter 10 CDMA Digital Modulation IS 95A Modulation ...
Страница 394: ...370 Chapter 12 Multitone Waveform Generator Applying Changes to an Active Multitone Signal ...
Страница 454: ...430 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Concepts Figure 15 9 Uplink Channel Structure ...
Страница 468: ...444 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Frame Structures ...
Страница 667: ...643 18 Troubleshooting ...
Страница 700: ...Index 676 Index ...