Agilent Technologies 1670E Series, Руководство пользователя

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Logic Analyzer Concepts
The Analyzer Hardware
RAM
Consisting of five 256Kx16 VRAM ICs and RAM addressing circuitry,
the RAM stores the desired patterns that appear at the module output.
The RAM addressing circuitry is merely a counter which addresses the
pattern locations in RAM. When the end of the vector listing is reached,
the addressing circuitry is loaded from the loop register with the
address of the first vector of the listing to provide an uninterrupted
vector loop. The RAM output is sent to the Output Driver circuit where
the patterns are presented in a logic configuration usable by the output
pods.
Output Driver
The output driver circuit is made up of a series of latch/logic translators
and multiplexers. The latch/translators convert the working-level TTL
signals to output-level ECL signals for each channel. The ECL-level
signals are then directed to the multiplexers.
The multiplexers, one per channel, direct the programmed data
patterns to the output channels. The single-ended ECL-level signals
are converted to differential signals which are routed to the output
cables and to the pods. Note that the differential ECL output signal of
the pattern generator module is not suitable to directly drive ECL
circuitry.
Clock Circuit
The clock circuit paces the loop register, the RAM address circuitry,
and the multiplexers in the output driver according to the desired data
rate. A 200 MHz clock source is directed through a divider circuit
which provides a 100 MHz and 50 MHz clock in addition to 200 MHz.
The 200 MHz, 100 MHz, 50 MHz and external clock signals are routed
to a clock select multiplexer. The output of the multiplexer, which
represents the user-selected clocking rate, is distributed to the above
listed subcircuits.