Advantech POC127, Руководство пользователя

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POC-127 User Manual 16
3.1 Introduction
The POC-127 uses the Intel® Atom
TM
Processor N400 series (code named Pinev-
iew-M single-core processor) referred as the processor and Intel® I/O Controller Hub
8 (ICH8) Family Express Chipset referred as the chipset.
Processor features:

The processor is built on 45-nanometer Hi-K process technology

The processor is designed for a two-chip platform as opposed to the traditional
three-chip platforms (processor, GMCH, and ICH)

On die, primary 32-kB instructions cache and 24-kB write-back data cache

Intel® Hyper-Threading Technology (2 threads per core)

Single-core processors have on-die 512KB, 8-way L2 cache; dual-core proces-
sors have on-die 2 x 512KB, 8-way L2 cache

Supports IA 32-bit and Intel 64 architecture

Intel® Streaming SIMD Extensions 2 and 3 (SSE2 and SSE3) and Supplemen-
tal Streaming SIMD Extensions 3 (SSSE3) support

Micro-FCBGA8 packaging technologies

Thermal management support via Intel Thermal Monitor 1 (TM1)
Thermal Monitor 2 (TM2)

Supports C-state of C0/C1(E)/C2(E)/C4(E)

Enhanced Intel SpeedStep Technology (EIST)

Supports L2 dynamic cache sizing

Execute Disable Bit support for enhanced security
Memory features:

Support DDR2 SDRAMs
– Support for DDR2 at data transfer rate of 667 MT/s
– One channel of DDR2 memory (consists of 64-bit of data lines):

Maximum of two SO-DIMMs in Raw Card-A or Raw Card-C format
– I/O Voltage of 1.8 V for DDR2
– Non-ECC, unbuffered DDR2 SO-DIMMs only
– 512-Mb, 1-Gb and 2-Gb DDR2 DRAM technologies supported
– Maximum of 2-GB memory capacity supported:

Maximum of 1-GB memory capacity on one SO-DIMM or Memory Down
* Due to standard PC architecture, a certain amount of memory is reserved for sys-
tem usage and therefore the actual memory size is less than the stated amount.
Direct media interface features:

Compliant to Direct Media Interface (DMI)

Supports 2 lanes in each direction, point-to-point DMI interface to the chipset

Raw bit-rate on the data pins of 2.5Gb/s, resulting in a real bandwidth per pair of
250MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance

Maximum theoretical bandwidth on interface of 500MB/s in each direction simul-
taneously, for an aggregate of 1GB/s for the interface

100-MHz reference clock

64-bit downstream address (only 36-bit addressable from the processor)