Advantech PCI-1751, Руководство пользователя

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PCI-1751 User Manual 24
C.1 The Intel 8254
The PCI-1751 uses the Intel 8254 compatible programmable interval timer/counter.
The popular 8254 offers three independent 16-bit down counters. Each counter has a
clock input, control gate and an output. You can program each counter for maximum
count values from 2 to 65535.
The 8254 has a maximum input clock frequency of 10 MHz. The PCI-1751 provides
10 MHz input frequencies to the counter chip from an on-board crystal oscillator.
On the PCI-1751, the 8254 chip's Timer 0 and Timer 1 can be used separately or can
be cascaded to create a 32-bit programmable timer by setting JP2. When the clock
source of Timer 1 is from an external source, you can user Timer 0 and Timer 1 as
two independent 16-bit timers. When the clock source of Timer 1 is set to be the out-
put of Timer 0 (internal source) the two timers are cascaded as a 32-bit timer. When
the clock source of Timer 0 is provided externally by setting JP1, Timers 0 and 1 can
be used as a 32-bit event counter. Refer to section 2.3.3 for details of jumper set-
tings.
C.2 Counter Read/Write and Control Registers
The 8254 programmable interval timer uses four registers at addresses BASE+24,
BASE+25, BASE+26 and BASE+27 for read, write and control of counter functions.
Register functions appear below:
Since the 8254 counter uses a 16-bit structure, each section of read/ write data is
split into a least significant byte (LSB) and most signifi- cant byte (MSB). To avoid
errors it is important that you make read/ write operations in pairs and keep track of
the byte order.
The data format for the control register appears below:
Description:
SC1 & SC0 Select counter
Register Function
BASE+24 Counter 0 read/write
BASE+25 Counter 1 read/write
BASE+26 Counter 2 read/write
BASE+27 Counter control word
BASE+27 8254 control, standard mode
Bit D7 D6 D5 D4 D3 D2 D1 D0
Value SC1 SC0 RW1 RW0 M2 M1 M0 BCD
Counter SC1 SC0
0 0 0
1 0 1
2 1 0
Read-back command 1 1