Advantech PCI-1751, Руководство пользователя

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PCI-1751 User Manual 16
The gates of the counter/timers are internally pulled to +5 V when gate control is
enabled, but a user can also set it using the connector pins (CNT0_G, CNT1_G and
CNT2_G).
3.6 Interrupt Function
Introduction
Two lines in each I/O port (C0 and C4) and two of the three counter outputs (Timer 1
and Counter 2) are connected to the interrupt circuitry. The "Interrupt Control Regis-
ter" of the PCI-1751 controls how the combination of the 6 signals generates an inter-
rupt. Two interrupt request signals can be generated at the same time, and then the
software can service these two request signals by ISR. The dual interrupt sources
provide the card with more capability and flexibility.
IRQ Level
The IRQ level is set automatically by the PCI plug and play BIOS and is saved in the
PCI controller. There is no need for users to set the IRQ level. Only one IRQ level is
used by this card, although it has two interrupt sources.
Interrupt Control Register (Base + 32)
The "Interrupt Control Register" (Base + 32) controls the interrupt signal source,
edge and flag. Table 3-2 shows the bit map of the interrupt control register. The reg-
ister is a readable/writable register.
When writing to it, it is used as a control register, and when reading from it, it is used
as a status register.
M00 and M01: "mode bits" of port 0
M10 and M11: "mode bits" of port 1
E0, E1: triggering edge control bits
F0, F1: flag bits
Interrupt Source Control
The "mode bits" in the interrupt control register determine the allowable sources of
signals generating an interrupt. Bit 0 and bit 1 determine the interrupt source for port
0, and bit 4 and bit 5 determine the interrupt source for port 1, as indicated in Figure
below. Table 3.4 shows the relationship between an interrupt source and the values
in the mode bits.
Table 3.4: Interrupt Control Register Bit Map
Port # Port1 Port 0
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F1 E1 M11 M10 F0 E0 M01 M00