Advantech PCI-1751, Руководство пользователя

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15 PCI-1751 User Manual
Chapter 3
S
ignal Connections
3.5 Timer/Counter Operation
Introduction
The PCI-1751 includes one 8254 compatible programmable timer/counter chip which
provides three 16-bit counters, designated as Timer 0, Timer1 and Counter 2. Each
has 6 operation modes. Timer 0 and Timer 1 can be used separately or can be cas-
caded to create one 32-bit timer. Both Timer 1 and Counter 2 can generate interrupts
to the computer. Please refer to Appendix A for more information on the operation
modes of the counter chip. The block diagram of the timer/counter system is shown
in figure below.
Timer 0 & 1:
Two 16-bit Timers or One 32-bit Timer. Timer 0 and Timer 1 of the counter chip can
be used separately or can be cascaded to create a 32-bit programmable timer by set-
ting jumper JP2. By setting the clock source of Timer 1 to be an external source, you
can user Timer 0 and Timer 1 as two separate 16-bit timers. By setting the clock
source of Timer 1 to be the output of Timer 0 (internal source) these two timers are
cascaded to become one 32-bit timer. Setting jumper JP1 sets the clock source of
Timer 0 to be external, and this allows Timer 0 and Timer 1 to be cascaded into a 32-
bit event counter.
Counter 2:
Counter 2 can be a 16-bit timer or an event counter, selectable by setting JP3. When
the clock source is set for an internal source, Counter 2 is a 16-bit timer; when set as
an external source, then Counter 2 is an event counter. Counter 2 is set as mode 0
(interrupt on terminal count) in the driver provided by Advantech.
Timer/Counter Frequency and Interrupt:
The input clock frequency of the counter/timers is 10 MHz. The output of both Timer 1
and Counter 2 can generate interrupts for the system (refer to section 3.3). The max-
imum and minimum timer interrupt frequency is (10 MHz)/(2)=(5 MHz) and (10 MHz)/
(65535*65535)=0.002328 Hz, respectively.