Advantech MIC-3332, Руководство пользователя, Страница: 58 / 62

MIC-3332 User Manual 48
Register Address: IO address 44Dh
Register Name: GPIO Output Enable
Default Value: 00
Attribute: Read/Write
Note: GPIO setting is reserved.
Register Address: IO Address 44Eh
Register Name: IO Port 80 Status
Default Value: --
Attribute: Read Only
Register Address: IO Address 44Fh
Register Name: Dual BIOS Switch Register
Default Value: 00
Attribute: Read /Write
C.4 CPLD Upgrade
The CPLD can be update via JTAG interface.
C.4.1 JTAG Interface
The MIC-3332 supports JTAG update via debug pin header and Altra download
cable.
Bit Description Access
7-0 GPIO[7:0] Output Enable, RSVD R/W
Bit Description Access
7:0 IO Port 80 status RO
Bit Description Access
7:0
Dual BIOS Switch
00: Boot from BIOS1
01: Boot from BIOS2
Bit7-Manual Control
Other reserved
Example:
want to change flash BIOS1 ? need to set this register to 0x80;
If want to change flash BIOS2 ? need to set this register to
0x81.
RW
Table C.2: JTAG Interface
Connector pin Pin num Type Name Description
1 -- Power VCC 3.3V
2 F6 O FPGA_TDO
JTAG configuration pin
3 F5 I FPGA_TDI
4 G1 I FPGA_TMS
5 G2 O FPGA_TCK
6 -- Power GND GND