ADLINK Technology NuPRO-860 Series, Руководство пользователя

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40 Watchdog Timer
Figure 5-1: WDT Block Diagram
5.2 Configuration Registers
The Intel® 6300ESB ICH WDT, appears to BIOS as PCI Bus 0,
Device 29, Function 4, and has the standard set of PCI Configura-
tion register. The following describes the configuration registers.
Offset 10H: Base Address Register (BAR)
This register determines the memory base for WDT down-
counter setting. It will be used to set Preload value 1 register,
Preload value 2 register, General Interrupt Status register and
Reload register.
Preload Value 1 & 2 registers
These two registers are used to hold the preload value for the
WDT timer. Its value will be automatically transferred into the
down-counter every time the WDT enters the first and second
stage. Preload Value 1 register is located at Base + 00H and
Preload Value 2 register is located at Base + 04H. Only bit
[19:0] are settable.